Publications

Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma. Nonvolatile digital computing with ferroelectric FET. US Patent 10475514
Sumeet Kumar Gupta, Ahmedullah Aziz, Nikhil Shukla, Suman Datta, Xueqing Li, Vijaykrishnan Narayanan. Low power sense amplifier based on phase transition material. US Patent 10262714.
Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok Kim, Xueqing Li, Alexandre Schmid, Mahsa Shoaran, Unsuk Heo. Low power nanoelectronics. US Patent 9800094
Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta. Power rectifier using tunneling field effect transistor. US Patent 9391068
Vinay Saripalli, Dheeraj Mohata, Saurabh Mookherjea, Suman Datta, Vijaykrishnan Narayanan. TFET based 4T memory devices. US Patent 8638591
Jawar Singh, Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, Vijaykrishnan Narayanan. TFET based 6T SRAM cell. US Patent 8369134
M. Irick, Vijaykrishnan Narayanan, Hankyu Moon, Rajeev Sharma and Namsoon Jung. Apparatus and method for hardware implementation of object recognition from an image stream using artificial neural network, US Patent 8081816
M. Irick, Vijaykrishnan Narayanan, Hankyu Moon, Rajeev Sharma and Namsoon Jung. Apparatus and method for measuring audience data from image stream using dynamically-configurable hardware architecture. US Patent 8165386.

2023
Fine-to-Coarse Object Classification of Very Large Images Z Hakimi, V Narayanan 2023 IEEE International Conference on Image Processing (ICIP), 3498-3502
Multi-Exit Vision Transformer with Custom Fine-Tuning for Fine-Grained Image Recognition T Shen, C Lee, V Narayanan 2023 IEEE International Conference on Image Processing (ICIP), 2830-2834
Overview of Recent Advancements in Deep Learning and Artificial Intelligence V Narayanan, Y Cao, P Panda, N Reddy Challapalle, X Du, Y Kim, … Advances in Electromagnetics Empowered by Artificial Intelligence and Deep …
Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing MM Islam, S Alam, MA Jahangir, GS Rose, S Datta, V Narayanan, … arXiv preprint arXiv:2308.15756
Lightning Talk: Can memory technologies meet demands of data abundant applications? V Narayanan 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-2
Computational Associative Memory Powered by Ferroelectric Memory K Ni, Y Xiao, S Deng, V Narayanan 2023 Device Research Conference (DRC), 1-2
A Compact Ferroelectric 2T-(n+ 1) C Cell to Implement AND-OR Logic in Memory Y Xiao, Y Xu, S Deng, Z Zhao, S George, K Ni, V Narayanan 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1-6
Federated Learning with Spiking Neural Networks in Heterogeneous Systems SA Tumpa, S Singh, MFF Khan, MT Kandemir, V Narayanan, CR Das 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1-6
Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays T Li, H Zhong, S George, V Narayanan, L Shi, H Yang, X Li 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1-6
Fe-GCN: A 3D FeFET Memory Based PIM Accelerator for Graph Convolutional Networks H Zhong, Y Zhu, L Luo, T Li, C Wang, Y Xu, T Wang, Y Yu, V Narayanan, … 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1-6
ISVABI: In-Storage Video Analytics Engine with Block Interface Y Zheng, J Fixelle, P Huo, M Stan, M Mesnier, V Narayanan Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on …
WeightLock: A Mixed-Grained Weight Encryption Approach Using Local Decrypting Units for Ciphertext Computing in DNN Accelerators J Wang, Z Chen, Y Chen, Y Xu, T Wang, Y Yu, V Narayanan, S George, … 2023 IEEE 5th International Conference on Artificial Intelligence Circuits …
A Graphical Representation of Sensor Mapping for Machine Tool Fault Monitoring and Prognostics for Smart Manufacturing A Hanchate, PS Dave, A Tiwari, D Sagapuram, A Verma, SRT Kumara, … Smart and Sustainable Manufacturing Systems 7 (1), 82-110
Embedding Security into Ferroelectric FET Array via In-Situ Memory Operation Y Xu, Y Xiao, Z Zhao, F Müller, A Vardar, X Gong, S George, T Kämpfe, … arXiv preprint arXiv:2306.01863
Evaluating the Robustness of Complementary Channel Ferroelectric FETs Against Total Ionizing Dose Towards Radiation-Tolerant Embedded Nonvolatile Memory Z Jiang, Z Guo, X Luo, Z Faris, H Mulaosmanovic, V Narayanan, … TechRxiv
Token Adaptive Vision Transformer with Efficient Deployment for Fine-Grained Image Recognition C Lee, RB Brufau, K Ding, V Narayanan 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6
Eliminating Leakage in Volatile Memory with Anti-Ferroelectric Transistors H Zhong, Z Zheng, L Jiao, Z Zhou, C Sun, X Ma, V Narayanan, H Yang, …
Quasi-Nondestructive Read Out of Ferroelectric Capacitor Polarization by Exploiting a 2TnC Cell to Relax the Endurance Requirement Y Xiao, S Deng, Z Zhao, Z Faris, Y Xu, TJ Huang, V Narayanan, K Ni TechRxiv
FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge W Tang, M Lee, J Wu, Y Xu, Y Yu, Y Liu, K Ni, Y Wang, H Yang, … IEEE Transactions on Circuits and Systems I: Regular Papers
ASMCap: An Approximate String Matching Accelerator for Genome Sequence Analysis Based on Capacitive Content Addressable Memory H Zhong, Z Chen, W Huangfu, C Wang, Y Xu, T Wang, Y Yu, Y Liu, … arXiv preprint arXiv:2302.07478
STAR: Efficient SpatioTemporal Modeling for Action Recognition A Kumar, S Abrams, A Kumar, V Narayanan Circuits, Systems, and Signal Processing 42 (2), 705-723
Computationally efficient adaptive decompression for whole slide image processing Z Li, B Li, KW Eliceiri, V Narayanan Biomedical Optics Express 14 (2), 667-686
CMOS-compatible ising machines built using bistable latches coupled through ferroelectric transistor arrays A Mallick, Z Zhao, MK Bashar, S Alam, MM Islam, Y Xiao, Y Xu, A Aziz, … Scientific reports 13 (1), 1515
Extending Action Recognition in the Compressed Domain S Abrams, V Narayanan 2023 36th International Conference on VLSI Design and 2023 22nd …
Fusing In-Storage and Near-Storage Acceleration of Convolutional Neural Networks I Okafor, AK Ramanathan, NR Challapalle, Z Li, V Narayanan ACM Journal on Emerging Technologies in Computing Systems
2022
FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations Y Chen, Y Fu, M Lee, S George, Y Liu, V Narayanan, H Yang, X Li IEEE Transactions on Circuits and Systems II: Express Briefs 70 (4), 1605-1609
Voltage-controlled Cryogenic Boolean Logic Family Based on Ferroelectric SQUID S Alam, MS Hossain, K Ni, V Narayanan, A Aziz arXiv preprint arXiv:2212.08202
Compact ferroelectric programmable majority gate for compute-in-memory applications S Deng, M Benkhelifa, S Thomann, Z Faris, Z Zhao, TJ Huang, Y Xu, … 2022 International Electron Devices Meeting (IEDM), 36.7. 1-36.7. 4
On the write schemes and efficiency of FeFET 1T NOR array for embedded nonvolatile memory and beyond Y Xiao, Y Xu, Z Jiang, S Deng, Z Zhao, A Mallick, L Sun, R Joshi, X Li, … 2022 International Electron Devices Meeting (IEDM), 13.6. 1-13.6. 4
Ferroelectric fet based context-switching fpga enabling dynamic reconfiguration for adaptive deep learning machines Y Xu, Z Zhao, Y Xiao, T Yu, H Mulaosmanovic, D Kleimaier, S Duenkel, … arXiv preprint arXiv:2212.00089
On the Feasibility of 1T Ferroelectric FET Memory Array Z Jiang, Z Zhao, S Deng, Y Xiao, Y Xu, H Mulaosmanovic, S Duenkel, … IEEE Transactions on Electron Devices 69 (12), 6722-6730
Robust Multimodal Depth Estimation using Transformer based Generative Adversarial Networks MFF Khan, A Devulapally, S Advani, V Narayanan Proceedings of the 30th ACM International Conference on Multimedia, 3559-3568
Skipper: Enabling efficient SNN training through activation-checkpointing and time-skipping S Singh, A Sarma, S Lu, A Sengupta, MT Kandemir, E Neftci, … 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 565-581
Token and Head Adaptive Transformers for Efficient Natural Language Processing C Lee, MFF Khan, RB Brufau, K Ding, V Narayanan Proceedings of the 29th International Conference on Computational …
Ferroelectric FET-based strong physical unclonable function: a low-power, high-reliable and reconfigurable solution for Internet-of-Things security X Guo, X Ma, F Muller, K Ni, T Kampfe, Y Liu, V Narayanan, X Li arXiv preprint arXiv:2208.14678
CapCAM: A multilevel capacitive content addressable memory for high-accuracy and high-scalability search and compute applications X Ma, H Zhong, N Xiu, Y Chen, G Yin, V Narayanan, Y Liu, K Ni, H Yang, … IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (11 …
GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph Y Chen, G Dai, M Zhou, M Lee, N Challapalle, G Yin, Z Yang, Y Liu, … arXiv preprint arXiv:2208.08600
Cryogenic memory array based on ferroelectric squid and heater cryotron S Alam, MM Islam, MS Hossain, K Ni, V Narayanan, A Aziz 2022 Device Research Conference (DRC), 1-2
ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key J Wang, Z Chen, J Zhang, Y Xu, T Yu, E Ye, Z Zheng, H Yang, S George, … arXiv preprint arXiv:2206.08087
ISKEVA: in-SSD key-value database engine for video analytics applications Y Zheng, J Fixelle, N Challapalle, P Huo, Z Shen, Z Shao, M Stan, … Proceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on …
Asymmetric double-gate ferroelectric FET to decouple the tradeoff between thickness scaling and memory window Z Jiang, Y Xiao, S Chatterjee, H Mulaosmanovic, S Duenkel, S Soss, … 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …
A Scheduling Framework for Decomposable Kernels on Energy Harvesting IoT Edge Nodes S Jose, J Sampson, V Narayanan, MT Kandemir Proceedings of the Great Lakes Symposium on VLSI 2022, 91-96
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy J Wang, N Xiu, J Wu, Y Chen, Y Sun, H Yang, V Narayanan, S George, … 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 3408-3412
FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications Y Chen, Y Fu, M Lee, S George, Y Liu, V Narayanan, H Yang, X Li arXiv preprint arXiv:2205.11088
AIGuide: augmented reality hand guidance in a visual prosthetic S Lee, NDT Aldas, C Lee, MB Rosson, JM Carroll, V Narayanan ACM Transactions on Accessible Computing (TACCESS) 15 (2), 1-32
Hardware functional obfuscation with ferroelectric active interconnects T Yu, Y Xu, S Deng, Z Zhao, N Jao, YS Kim, S Duenkel, S Beyer, K Ni, … Nature communications 13 (1), 2235
Seeker: Synergizing mobile and energy harvesting wearable sensors for human activity recognition CS Mishra, J Sampson, MT Kandemir, V Narayanan arXiv preprint arXiv:2204.13106
Communication-Efficient -Means for Edge-Based Machine Learning H Lu, T He, S Wang, C Liu, M Mahdavi, V Narayanan, KS Chan, … IEEE Transactions on Parallel and Distributed Systems 33 (10), 2509-2523
Achieving Crash Consistency by Employing Persistent L1 Cache, A Ramanathan, S Shahri, Y Xiao, V Narayanan 2022 Design, Automation & Test in Europe Conference & Exhibition, 1407-1412
2021
Microprocessor at 50: Industry Leaders Speak LK John, V Narayanan IEEE Micro 41 (6), 13-15
Microprocessor at 50: A Time to Celebrate and Energize for the Future LK John, V Narayanan IEEE Micro 41 (6), 10-12
Intel Wins in Four Decades, but AMD Catches Up B Hanindhito, K Swaminathan, V Narayanan, LK John IEEE Micro 41 (6), 168-171
Sparse Vector-Matrix Multiplication Acceleration in Diode-Selected Crossbars N Jao, AK Ramanathan, J Sampson, V Narayanan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (12 …
Sparse to dense depth completion using a generative adversarial network with intelligent sampling strategies MFF Khan, ND Troncoso Aldas, A Kumar, S Advani, V Narayanan Proceedings of the 29th ACM International Conference on Multimedia, 5528-5536
DyTAN: Dynamic ternary content addressable memory using nanoelectromechanical relays H Zhong, S Cao, L Jiang, X An, V Narayanan, Y Liu, H Yang, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (11 …
Transformer-based machine learning for fast SAT solvers and logic synthesis F Shi, C Lee, MK Bashar, N Shukla, SC Zhu, V Narayanan arXiv preprint arXiv:2107.07116
Star: Sparse transformer-based action recognition F Shi, C Lee, L Qiu, Y Zhao, T Shen, S Muralidhar, T Han, SC Zhu, … arXiv preprint arXiv:2107.07089
Overview of ferroelectric memory devices and reliability aware design optimization S Deng, Z Zhao, S Kurinec, K Ni, Y Xiao, T Yu, V Narayanan Proceedings of the 2021 on Great Lakes Symposium on VLSI, 473-478
Ferroelectric-based Accelerators for Computationally Hard Problems MK Bashar, J Vaidya, RS Surya Kanthi, C Lee, F Shi, V Narayanan, … Proceedings of the 2021 on Great Lakes Symposium on VLSI, 485-489
CiM3D: Comparator-in-memory designs using monolithic 3-D technology for accelerating data-intensive applications AK Ramanathan, SS Rangachar, HT Govindarajan, JM Hung, CY Lee, … IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 7 …
Design space for scaling-in general purpose computing within the DDR DRAM hierarchy for map-reduce workloads SB Rai, A Sivasubramaniam, A Kumar, PV Rengasamy, V Narayanan, … Proceedings of the 18th ACM International Conference on Computing Frontiers …
Trends and opportunities for SRAM based in-memory and near-memory computation S Srinivasa, AK Ramanathan, J Sundaram, D Kurian, S Gopal, N Jain, … 2021 22nd International Symposium on Quality Electronic Design (ISQED), 547-552
CAPE: A content-addressable processing engine H Caminal, K Yang, S Srinivasa, AK Ramanathan, K Al-Hawaj, T Wu, … 2021 IEEE International Symposium on High-Performance Computer Architecture …
Origin: Enabling on-device intelligence for human activity recognition using energy harvesting wireless sensor networks CS Mishra, J Sampson, MT Kandemir, V Narayanan 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …
Resolution-Aware Deep Multi-View Camera Systems Z Hakimi, V Narayanan 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 414-417
Predictive Modeling of Ferroelectric Tunnel Junctions for Memory and Analog Weight Cell Applications Y Xiao, S Deng, Z Zhao, V Narayanan, K Ni 2021 IEEE International Electron Devices Meeting (IEDM), 15.5.1-15.5.4
PowerPrep: A power management proposal for user-facing datacenter workloads. VN Vineetha Govindaraj, Sumitha George, Mahmut Kandemir, John Sampson 2021 IEEE International Conference on Networking, Architecture and Storage …
2020
Monolithic 3D+-IC based massively parallel compute-in-memory macro for accelerating database and machine learning primitives AK Ramanathan, SS Rangachar, JM Hung, CY Lee, CX Xue, SP Huang, … 2020 IEEE International Electron Devices Meeting (IEDM), 28.5. 1-28.5. 4
Low power sense amplifier based on phase transition material SK Gupta, A Ahmedullah, N Shukla, S Datta, X Li, V Narayanan US Patent 10,839,880
FARM: A flexible accelerator for recurrent and memory augmented neural networks N Challapalle, S Rampalli, N Jao, A Ramanathan, J Sampson, … Journal of Signal Processing Systems 92, 1247-1261
AIGuide: An augmented reality hand guidance application for people with visual impairments ND Troncoso Aldas, S Lee, C Lee, MB Rosson, JM Carroll, V Narayanan Proceedings of the 22nd International ACM SIGACCESS Conference on Computers …
Look-up table based energy efficient processing in cache support for neural network acceleration AK Ramanathan, GS Kalsi, S Srinivasa, TM Chandran, KR Pillai, OJ Omer, … 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …
Optimization of Intercache Traffic Entanglement in Tagless Caches With Tiling Opportunities SRSS Chongala, S George, HT Govindarajan, J Kotra, M Mutyam, … IEEE Transactions on Computer-Aided Design of Integrated Circuits and …
Design insights of non-volatile processors and accelerators in energy harvesting systems K Qiu, M Zhao, Z Jia, J Hu, CJ Xue, K Ma, X Li, Y Liu, V Narayanan Proceedings of the 2020 on Great Lakes Symposium on VLSI, 369-374
IMC-sort: In-memory parallel sorting architecture using hybrid memory cube Z Li, N Challapalle, AK Ramanathan, V Narayanan Proceedings of the 2020 on Great Lakes Symposium on VLSI, 45-50
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface M Lee, W Tang, B Xue, J Wu, M Ma, Y Wang, Y Liu, D Fan, V Narayanan, … Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …
Learning to quantize deep neural networks: A competitive-collaborative approach MFF Khan, MM Kamani, M Mahdavi, V Narayanan 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6
DoubtNet: Using Semantic Context to Enable Adaptive Inference for the IoT E Homan, C Lee, J Sampson, J Sustersic, V Narayanan 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 586-591
X-VS: Crossbar-Based Processing-in-Memory Architecture for Video Summarization N Challapalle, M Chandran, S Rampalli, V Narayanan 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 592-597
Joint coreset construction and quantization for distributed machine learning H Lu, C Liu, S Wang, T He, V Narayanan, KS Chan, S Pasteris 2020 IFIP Networking Conference (Networking), 172-180
Robust coreset construction for distributed machine learning H Lu, MJ Li, T He, S Wang, V Narayanan, KS Chan IEEE Journal on Selected Areas in Communications 38 (10), 2400-2417
Nebula: a neuromorphic spin-based ultra-low power architecture for snns and anns S Singh, A Sarma, N Jao, A Pattnaik, S Lu, K Yang, A Sengupta, … 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …
GaaS-X: Graph analytics accelerator supporting sparse data representation using crossbar architectures N Challapalle, S Rampalli, L Song, N Chandramoorthy, K Swaminathan, … 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …
Integrated CAM-RAM functionality using ferroelectric FETs S George, N Jao, AK Ramanathan, X Li, SK Gupta, J Sampson, … 2020 21st International Symposium on Quality Electronic Design (ISQED), 81-86
Psb-rnn: A processing-in-memory systolic array architecture using block circulant matrices for recurrent neural networks N Challapalle, S Rampalli, M Chandran, G Kalsi, S Subramoney, … 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 180-185
ResiRCA: A resilient energy harvesting ReRAM crossbar-based accelerator for intelligent embedded processors K Qiu, N Jao, M Zhao, CS Mishra, G Gudukbay, S Jose, J Sampson, … 2020 IEEE International Symposium on High Performance Computer Architecture …
Mixed precision Quantization scheme for re-configurable ReRAM crossbars targeting different energy harvesting scenarios MFF Khan, NA Jao, C Shuai, K Qiu, M Mahdavi, V Narayanan Internet of Things. A Confluence of Many Disciplines: Second IFIP …
Nonvolatile processor architecture exploration for energy-harvesting application scenarios K Ma, S Li, V Narayanan, Y Xie Embedded, Cyber-Physical, and IoT Systems: Essays Dedicated to Marilyn Wolf …
2019
Nonvolatile digital computing with ferroelectric FET X Li, S George, J Sampson, S Gupta, S Datta, V Narayanan, K Ma US Patent 10,475,514
Training UUV navigation and contact avoidance with reinforcement learning E Homan, S Davis, K Hall, S McClure, J Sustersic, V Narayanan OCEANS 2019 MTS/IEEE SEATTLE, 1-5
Adaptive neural network architectures for power aware inference S Anderson, N Challapalle, J Sampson, V Narayanan IEEE Design & Test 37 (2), 66-75
A FerroFET-based in-memory processor for solving distributed and iterative optimizations via least-squares method I Yoon, M Chang, K Ni, M Jerry, S Gangopadhyay, GH Smith, T Hamam, … IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 5 …
Technology-assisted computing-in-memory design for matrix multiplication workloads N Jao, S Srivinasa, A Ramanathan, M Kim, J Sampson, V Narayanan 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 1-6
Monolithic 3D⁺ -IC based Reconfigurable Compute-in-Memory SRAM Macro S Srinivasa, YN Tu, X Si, CX Xue, CY Lee, FK Hsueh, CH Shen, JM Shieh, … 2019 Symposium on VLSI Technology, T32-T33
Context-aware convolutional neural network over distributed system in collaborative computing J Choi, Z Hakimi, PW Shin, J Sampson, V Narayanan Proceedings of the 56th Annual Design Automation Conference 2019, 1-6
Monolithic-3D integration augmented design techniques for computing in SRAMs S Srinivasa, WH Chen, YN Tu, MF Chang, J Sampson, V Narayanan 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5
Programmable non-volatile memory design featuring reconfigurable in-memory operations N Jao, AK Ramanathan, A Sengupta, J Sampson, V Narayanan 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5
Low power sense amplifier based on phase transition material SK Gupta, A Ahmedullah, N Shukla, S Datta, X Li, V Narayanan US Patent 10,262,714
Design of 2T/cell and 3T/cell nonvolatile memories with emerging ferroelectric FETs X Li, J Wu, K Ni, S George, K Ma, J Sampson, SK Gupta, Y Liu, H Yang, … IEEE Design & Test 36 (3), 39-45
ROBIN: Monolithic-3D SRAM for enhanced robustness with in-memory computation support S Srinivasa, AK Ramanathan, X Li, WH Chen, SK Gupta, MF Chang, … IEEE Transactions on Circuits and Systems I: Regular Papers 66 (7), 2533-2545
SRAMs and DRAMs with separate read–write ports augmented by phase transition materials Z Shen, S Srinivasa, A Aziz, S Datta, V Narayanan, SK Gupta IEEE Transactions on Electron Devices 66 (2), 929-937
Sensing in Ferroelectric Memories and Flip-Flops A Aziz, SK Thirumala, D Wang, S George, X Li, S Datta, V Narayanan, … Sensing of Non-Volatile Memory Demystified, 47-80
Emerging steep-slope devices and circuits: Opportunities and challenges X Li, MS Kim, S George, A Aziz, M Jerry, N Shukla, J Sampson, S Gupta, … Beyond-CMOS Technologies for Next Generation Computer Design, 195-230
2018
Computing with networks of oscillatory dynamical systems A Raychowdhury, A Parihar, GH Smith, V Narayanan, G Csaba, M Jerry, … Proceedings of the IEEE 107 (1), 73-89
Nagarajan Ranganathan (March 30, 1961-October 25, 2018) In Memoriam V Narayanan IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 26 (12 …
Ultra-Low Power 3D NC-FinFET-based Monolithic 3D⁺ -IC with Computing-in-Memory for Intelligent IoT Devices FK Hsueh, WH Chen, KS Li, CH Shen, JM Shieh, CY Lee, BY Chen, … 2018 IEEE International Electron Devices Meeting (IEDM), 15.1. 1-15.1. 4
Emerging reconfigurable nanotechnologies: Can they support future electronics? S Rai, S Srinivasa, P Cadareanu, X Yin, XS Hu, PE Gaillardon, … 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8
Analysis of DIBL effect and negative resistance performance for NCFET based on a compact SPICE model Y Liang, X Li, SK Gupta, S Datta, V Narayanan IEEE Transactions on Electron Devices 65 (12), 5525-5529
MDACache: Caching for multi-dimensional-access memories S George, MJ Liao, H Jiang, JB Kotra, MT Kandemir, J Sampson, … 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …
Heuristic approximation of early-stage CNN data representation for vision intelligence systems J Choi, J Sampson, V Narayanan 2018 IEEE 36th International Conference on Computer Design (ICCD), 218-225
Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms PA Zientara, J Sampson, V Narayanan 2018 31st IEEE International System-on-Chip Conference (SOCC), 186-191
HeTERO: Hybrid Topology Exploration for RF-Based On-Chip Networks S Eachempati, R Das, V Narayanan, Y Xie, S Datta, CR Das Communication Architectures for Systems-on-Chip, 231-278
IAA: Incidental approximate architectures for extremely energy-constrained energy harvesting scenarios using IoT nonvolatile processors K Ma, J Li, X Li, Y Liu, Y Xie, M Kandemir, J Sampson, V Narayanan IEEE Micro 38 (4), 11-19
Influence of body effect on sample-and-hold circuit design using negative capacitance FET Y Liang, X Li, S George, S Srinivasa, Z Zhu, SK Gupta, S Datta, … IEEE Transactions on Electron Devices 65 (9), 3909-3914
A monolithic-3D SRAM design with enhanced robustness and in-memory computation support S Srinivasa, AK Ramanathan, X Li, WH Chen, FK Hsueh, CC Yang, … Proceedings of the International Symposium on Low Power Electronics and …
Harnessing emerging technology for compute-in-memory support N Jao, AK Ramanathan, S Srinivasa, S George, J Sampson, V Narayanan 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 447-452
A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs J Choi, S Srinivasa, Y Tanabe, J Sampson, V Narayanan 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 22-27
A FeFET based processing-in-memory architecture for solving distributed least-square optimizations I Yoon, M Chang, K Ni, M Jerry, S Gangopadhyay, G Smith, T Hamam, … 2018 76th Device Research Conference (DRC), 1-2
Stochastic functional verification of dnn design through progressive virtual dataset generation J Choi, KM Irick, J Hardin, W Qiu, A Yuille, J Sampson, V Narayanan 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5
Lowering area overheads for FeFET-based energy-efficient nonvolatile flip-flops X Li, S George, Y Liang, K Ma, K Ni, A Aziz, SK Gupta, J Sampson, … IEEE Transactions on Electron Devices 65 (6), 2670-2674
NEOFog: Nonvolatility-exploiting optimizations for fog computing K Ma, X Li, MT Kandemir, J Sampson, V Narayanan, J Li, T Wu, Z Wang, … Proceedings of the Twenty-Third International Conference on Architectural …
Symmetric 2-d-memory access to multidimensional data S George, X Li, MJ Liao, K Ma, S Srinivasa, K Mohan, A Aziz, J Sampson, … IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (6 …
Compact 3-D-SRAM memory with concurrent row and column data access capability using sequential monolithic 3-D integration S Srinivasa, X Li, MF Chang, J Sampson, SK Gupta, V Narayanan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (4), 671-683
Drones as collaborative sensors for image recognition PA Zientara, J Choi, J Sampson, V Narayanan 2018 IEEE International Conference on Consumer Electronics (ICCE), 1-4
Tutorial T1B: Emerging Computational Devices, Architectures and Computational Models V Narayanan, A Raychowdhury, SK Gupta 2018 31st International Conference on VLSI Design and 2018 17th …
2017
Compact 3D-SRAM Memory with Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3D integration J Sampson, SK Gupta, V Narayanan
TSV-free FinFET-based Monolithic 3D⁺-IC with computing-in-memory SRAM cell for intelligent IoT devices FK Hsueh, HY Chiu, CH Shen, JM Shieh, YT Tang, CC Yang, HC Chen, … 2017 IEEE International Electron Devices Meeting (IEDM), 12.6. 1-12.6. 4
Low power nanoelectronics H Liu, R Vaddi, V Narayanan, S Datta, MS Kim, X Li, A Schmid, … US Patent 9,800,094
Welcome message from the general co-chairs V Narayanan, B Guo Proceedings-2016 13th International Conference on Embedded Software and …
Incidental computing on IoT nonvolatile processors K Ma, X Li, J Li, Y Liu, Y Xie, J Sampson, MT Kandemir, V Narayanan Proceedings of the 50th Annual IEEE/ACM International Symposium on …
An accuracy tunable non-Boolean co-processor using coupled nano-oscillators N Gala, S Krithivasan, WY Tsai, X Li, V Narayanan, V Kamakoti ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (1), 1-28
Device-circuit analysis of ferroelectric FETs for low-power logic S Gupta, M Steiner, A Aziz, V Narayanan, S Datta, SK Gupta IEEE Transactions on Electron Devices 64 (8), 3092-3100
Improving FPGA design with monolithic 3D integration using high dense inter-stack via SR Srinivasa, K Mohan, WH Chen, KH Hsu, X Li, MF Chang, SK Gupta, … 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 128-133
Enabling energy-efficient nonvolatile computing with negative capacitance FET X Li, J Sampson, A Khan, K Ma, S George, A Aziz, SK Gupta, … IEEE Transactions on Electron Devices 64 (8), 3452-3458
Low power current sense amplifier based on phase transition material A Aziz, X Li, N Shukla, S Datta, MF Chang, V Narayanan, SK Gupta 2017 75th Annual Device Research Conference (DRC), 1-2
Co-training of feature extraction and classification using partitioned convolutional neural networks WY Tsai, J Choi, T Parija, P Gomatam, C Das, J Sampson, V Narayanan Proceedings of the 54th Annual Design Automation Conference 2017, 1-6
Design of nonvolatile SRAM with ferroelectric FETs for energy-efficient backup and restore X Li, K Ma, S George, WS Khwa, J Sampson, S Gupta, Y Liu, MF Chang, … IEEE Transactions on Electron Devices 64 (7), 3037-3040
Advancing nonvolatile computing with nonvolatile NCFET latches and flip-flops X Li, S George, K Ma, WY Tsai, A Aziz, J Sampson, SK Gupta, MF Chang, … IEEE Transactions on Circuits and Systems I: Regular Papers 64 (11), 2907-2919
Maximum energy efficiency tracking circuits for converter-less energy harvesting sensor nodes Y Sun, Z Yuan, Y Liu, X Li, Y Wang, Q Wei, Y Wang, V Narayanan, … IEEE Transactions on Circuits and Systems II: Express Briefs 64 (6), 670-674
Dynamic power and energy management for energy harvesting nonvolatile processor systems K Ma, X Li, H Liu, X Sheng, Y Wang, K Swaminathan, Y Liu, Y Xie, … ACM Transactions on Embedded Computing Systems (TECS) 16 (4), 1-23
The third eye: A shopping assistant for the visually impaired JM Carroll, M McManus, S Lee, PA Zientara, V Narayanan Proceedings of the 2017 CHI Conference Extended Abstracts on Human Factors …
Nonvolatile processors: Why is it trending? F Su, K Ma, X Li, T Wu, Y Liu, V Narayanan Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …
Harnessing ferroelectrics for non-volatile memories and logic SK Gupta, D Wang, S George, A Aziz, X Li, S Datta, V Narayanan 2017 18th International Symposium on Quality Electronic Design (ISQED), 29-34
Third eye: A shopping assistant for the visually impaired PA Zientara, S Lee, GH Smith, R Brenner, L Itti, MB Rosson, JM Carroll, … Computer 50 (2), 16-24
Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors K Ma, X Li, SR Srinivasa, Y Liu, J Sampson, Y Xie, V Narayanan 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 678-683
Dynamic diagnosis for defective reconfigurable single-electron transistor arrays YJ Li, CY Huang, CC Wu, YC Chen, CY Wang, S Datta, V Narayanan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …
A Multitask Grocery Assistance System for the Visually Impaired Smart glasses, gloves, and shopping carts provide auditory and tactile feedback P Zientara, S Advani, N Shukla, I Okafor, K Irick, J Sampson, S Datta, … IEEE Consumer Electronics Magazine 6 (1), 73-81
Enabling Internet-of-Things with opportunities brought by emerging devices, circuits and architectures X Li, K Ma, S George, J Sampson, V Narayanan VLSI-SoC: System-on-Chip in the Nanoscale Era–Design, Verification and …
2016
A multitask grocery assist system for the visually impaired: Smart glasses, gloves, and shopping carts provide auditory and tactile feedback S Advani, P Zientara, N Shukla, I Okafor, K Irick, J Sampson, S Datta, … IEEE Consumer Electronics Magazine 6 (1), 73-81
Always-on speech recognition using truenorth, a reconfigurable, neurosynaptic processor WY Tsai, DR Barch, AS Cassidy, MV DeBole, A Andreopoulos, … IEEE Transactions on Computers 66 (6), 996-1007
Correlated material enhanced SRAMs with robust low power operation S Srinivasa, A Aziz, N Shukla, X Li, J Sampson, S Datta, JP Kulkarni, … IEEE Transactions on Electron Devices 63 (12), 4744-4752
Area-aware decomposition for single-electron transistor arrays CH Ho, YC Chen, CY Wang, CY Huang, S Datta, V Narayanan ACM Transactions on Design Automation of Electronic Systems (TODAES) 21 (4 …
Computing with Coupled Dynamical Systems N Shukla, S Datta, A Parihar, V Narayanan, A Raychowdhury CNNA 2016; 15th International Workshop on Cellular Nanoscale Networks and …
Ferroelectric transistor based non-volatile flip-flop D Wang, S George, A Aziz, S Datta, V Narayanan, SK Gupta Proceedings of the 2016 international symposium on low power electronics and …
LATTE: Low-power audio transform with truenorth ecosystem WY Tsai, DR Barch, AS Cassidy, MV DeBole, A Andreopoulos, … 2016 International Joint Conference on Neural Networks (IJCNN), 4270-4277
Power rectifier using tunneling field effect transistor H Liu, R Vaddi, V Narayanan, S Datta US Patent 9,391,068
Device circuit co design of FEFET based logic for low voltage processors S George, A Aziz, X Li, MS Kim, S Datta, J Sampson, S Gupta, … 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 649-654
Nanotechnology-inspired future computing, challenges and opportunities Y Chen, Q Wu, S Basu, JJ Candelaria, D Hammerstrom, D Mountain, … 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). Bochum, Germany
Phase transition oxide neuron for spiking neural networks M Jerry, W Tsai, B Xie, X Li, V Narayanan, A Raychowdhury, S Datta 2016 74th Annual Device Research Conference (DRC), 1-2
Ultra low power coupled oscillator arrays for computer vision applications N Shukla, WY Tsai, M Jerry, M Barth, V Narayanan, S Datta 2016 IEEE symposium on VLSI technology, 1-2
Nonvolatile memory design based on ferroelectric FETs S George, K Ma, A Aziz, X Li, A Khan, S Salahuddin, MF Chang, S Datta, … Proceedings of the 53rd Annual Design Automation Conference, 1-6
Nonvolatile processor architectures: Efficient, reliable progress with unstable power K Ma, X Li, K Swaminathan, Y Zheng, S Li, Y Liu, Y Xie, JJ Sampson, … IEEE Micro 36 (3), 72-83
Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells MS Kim, W Cane-Wissing, X Li, J Sampson, S Datta, SK Gupta, … ACM Journal on Emerging Technologies in Computing Systems (JETC) 12 (4), 1-23
Architecture and design flow optimizations for power-aware FPGAs A Gayasen, V Narayanan The VLSI Handbook: Second Edition, 20.1-20.15
Compiler-directed communication energy optimizations for microsensor networks I Kadayif, M Kandemir, A Choudhary, M Karakoy, N Vijaykrishnan, … Distributed Sensor Networks, 655-678
3D IC DESIGN AUTOMATION CONSIDERING DYNAMIC POWER AND THERMAL INTEGRITY H Yu, X Huang 3D Integration for VLSI Systems, 335
Designing energy-aware sensor systems N Vijaykrishnan, MJ Irwin, M Kandemir, L Li, G Chen, B Kang Distributed Sensor Networks, 595-608
An energy-aware approach for sensor data communication H Saputra, N Vijaykrishnan, M Kandemir, RR Brooks, MJ Irwin Distributed Sensor Networks, 639-653
A saliency-driven LCD power management system Y Xiao, S Advani, D Shin, N Chang, JJ Sampson, V Narayanan IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (8 …
Enabling new computation paradigms with HyperFET-an emerging device WY Tsai, X Li, M Jerry, B Xie, N Shukla, H Liu, N Chandramoorthy, … IEEE Transactions on Multi-Scale Computing Systems 2 (1), 30-48
Diagnosis and synthesis for defective reconfigurable single-electron transistor arrays CY Huang, YJ Li, CW Liu, CY Wang, YC Chen, S Datta, V Narayanan IEEE transactions on very large scale integration (vlsi) systems 24 (6 …
Towards a unified multiresolution vision model for autonomous ground robots J Sustersic, B Wyble, S Advani, V Narayanan Robotics and Autonomous Systems 75, 221-232
Sensor Network Security with Random Key Predistribution L Zhao, RR Brooks, B Pillai, PY Govindaraju, M Pirretti, V Narayanan, … Distributed Sensor Networks: Second Edition: Sensor Networking and …
Exploration of Hardware Acceleration for a Neuromorphic Visual Classification System IJ Okafor, MN Scholar, KM Irick, V Narayanan The Penn State McNair Journal, 59

Z Shen, S Srinivasa, A Aziz, S Datta, V Narayanan, SK Gupta. SRAMs and DRAMs With Separate Read–Write Ports Augmented by Phase Transition Materials. IEEE Transactions on Electron Devices 66 (2), 929-937 (2019)
Xueqing Li, Juejian Wu, Kai Ni, Sumitha George, Kaisheng Ma, John Sampson, Sumeet Kumar Gupta, Yongpan Liu, Huazhong Yang, Suman Datta, Vijaykrishnan Narayanan. Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs. IEEE Design & Test 36(3): 39-45 (2019)
Arijit Raychowdhury, Abhinav Parihar, Gus Henry Smith, Vijaykrishnan Narayanan, György Csaba, Matthew Jerry, Wolfgang Porod, Suman Datta. Computing With Networks of Oscillatory Dynamical Systems. Proceedings of the IEEE 107(1): 73-89 (2019)
Srivatsa Rangachar Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei-Hao Chen, Sumeet Kumar Gupta, Meng-Fan Chang, Swaroop Ghosh, Jack Sampson, Vijaykrishnan Narayanan. ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support. IEEE Trans. on Circuits and Systems 66-I(7): 2533-2545 (2019)
Kaisheng Ma, Jinyang Li, Xueqing Li, Yongpan Liu, Yuan Xie, Mahmut T. Kandemir, Jack Sampson, Vijaykrishnan Narayanan. IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors. IEEE Micro 38(4): 11-19 (2018)
Xueqing Li, Sumitha George, Kaisheng Ma, Kai Ni, Ahmedullah Aziz, Sumeet Gupta, John Sampson, Meng-Fan Chang, Yongpan Liu, Huazhong Yang, Suman Datta, and Vijaykrishnan Narayanan. Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops. IEEE Transactions on Electron Devices, accepted.
Sumitha George, Xueqing Li, Minli Julie Liao, Kaisheng Ma, Srivatsa Srinivasa, Karthik Mohan, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, and Vijaykrishnan Narayanan. Symmetric 2-D-Memory Access to Multidimensional Data. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, doi: 10.1109/TVLSI.2018.2801302.
Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, Kamakoti: An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. JETC 14(1): 1:1-1:28 (2018)
Srivatsa Rangachar Srinivasa, Xueqing Li, Meng-Fan Chang, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan: Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration. IEEE Trans. VLSI Syst. 26(4): 671-683 (2018)
Xueqing Li; John Sampson; Asif Khan; Kaisheng Ma; Sumitha George; Ahmedullah Aziz; Sumeet Kumar Gupta; Sayeef Salahuddin; Meng-Fan Chang; Suman Datta; Vijaykrishnan Narayanan. Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET. IEEE Transactions on Electron Devices 2017, 64(8): 3452 – 3458
Shreya Gupta; Mark Steiner; Ahmedullah Aziz; Vijaykrishnan Narayanan; Suman Datta; Sumeet Kumar Gupta. Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic. IEEE Transactions on Electron Devices. 2017, 64(8): 3092 – 3100
Xueqing Li; Kaisheng Ma; Sumitha George; Win-San Khwa; John Sampson; Sumeet Gupta; Yongpan Liu; Meng-Fan Chang; Suman Datta; Vijaykrishnan Narayanan. Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore. IEEE Transactions on Electron Devices. 2017. 64(7): 3037 – 3040
Xueqing Li; Sumitha George; Kaisheng Ma; Wei-Yu Tsai; Ahmedullah Aziz; John Sampson; Sumeet Kumar Gupta; Meng-Fan Chang; Yongpan Liu; Suman Datta; Vijaykrishnan Narayanan. Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops. IEEE Transactions on Circuits and Systems I: Regular Papers. 2017, 13 pages.
Peter A. Zientara, Sooyeon Lee, Gus H. Smith, Rorry Brenner, Laurent Itti, Mary Beth Rosson, John M. Carroll, Kevin M. Irick, Vijaykrishnan Narayanan. Third Eye: A Shopping Assistant for the Visually Impaired. IEEE Computer 50(2): 16-24 (2017)
Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan. Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. VLSI Syst. 25(4): 1477-1489 (2017)
Xiao, Y., Advani, S., Shin, D., Chang, N., Sampson, J., & Narayanan, V. (Author) (2016). A Saliency-Driven LCD Power Management System. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(8), 2689–2702. (First and second author supervised)
Tsai, W.-Y., Barch, D., Cassidy, A., Debole, M., Andreopoulos, A., Jackson, B., Flickner, M., Arthur, J., Modha, D., Sampson, J., & Narayanan, V. (Author) (2016). Always-on Speech Recognition using TrueNorth, a Reconfigurable, Neurosynaptic Processor. IEEE Transactions on Computers(99). (First Author co-supervised)
Ho, C.-H., Chen, Y.-C., Wang, C.-Y., Huang, C.-Y., Datta, S., & Narayanan, V. (Author) (2016). Area-Aware Decomposition for Single-Electron Transistor Arrays. ACM Transactions on Design Automation of Electronic Systems (TODAES), 21(4), 70.
Kim, M. S., Cane-Wissing, W., Li, X., Sampson, J., Datta, S., Gupta, S., & Narayanan, V. (Author) (2016). Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells. ACM Journal on Emerging Technologies in Computing Systems (JETC), 12(4), 38. (First Author supervised)
Srinivasa, S., Aziz, A., Shukla, N., Li, X., Sampson, J., Datta, S., Kulkarni, J. P., Narayanan, V. (Author), & Gupta, S. (2016). Correlated Material Enhanced SRAMs With Robust Low Power Operation. IEEE Transactions on Electron Devices, 63(12), 4744–4752. (First Author co-supervised)
Huang, C.-Y., Li, Y.-J., Liu, C.-W., Wang, C.-Y., Chen, Y.-C., Datta, S., & Narayanan, V. (Author) (2016). Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(6), 2321–2334.
Tsai, W.-Y., Li, X., Jerry, M., Xie, B., Shukla, N., Liu, H., Chandramoorthy, N., Cotter, M., Raychowdhury, A., Chiarulli, D. M., Levitan, S. P., Datta, S., Sampson, J., Ranganathan, N., & Narayanan, V. (2016). Enabling new computation paradigms with hyperFET-an emerging device. IEEE Transactions on Multi-Scale Computing Systems, 2(1), 30–48. (First author supervised)
Kim, M. S., Li, X., Liu, H., Sampson, J., Datta, S., & Narayanan, V. (Author) (2016). Exploration of low-power high-SFDR current-steering D/A converter design using steep-slope heterojunction Tunnel FETs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(6), 2299–2309. (First author supervised)
Sun, Y., Yuan, Z., Liu, Y., Li, X., Wang, Y., Wei, Q., Wang, Y., Narayanan, V. (Author), & Yang, H. (2016). Maximum Energy Efficiency Tracking Circuits for Converter-less Energy Harvesting Sensor Nodes. IEEE Transactions on Circuits and Systems II: Express Briefs. (Fourth author supervised)
Ma, K., Li, X., Swaminathan, K., Zheng, Y., Li, S., Liu, Y., Xie, Y., Sampson, J., & Narayanan, V. (Author) (2016). Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power. IEEE Micro, 36(3), 72–83. (First Author co-supervised, second author supervised)
Sustersic, J., Wyble, B., Advani, S., & Narayanan, V. (Author) (2016). Towards a unified multiresolution vision model for autonomous ground robots. Robotics and Autonomous Systems, 75, 221–232. http://dx.doi.org/10.1016/j.robot.2015.09.031. (Third author supervised)
Kaisheng Ma, Xueqing Li, Shuangchen Li, Yongpan Liu, John (Jack) Morgan Sampson, Yuan Xie, Vijaykrishnan Narayanan:Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications. IEEE Micro 35(5): 32-40 (2015) (First Author co-supervised, second author supervised)
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan: Synthesis for Width Minimization in the Single-Electron Transistor Array. IEEE Trans. VLSI Syst. 23(12): 2862-2875 (2015)
Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, and Yuan Xie, “Optimizing the NoC Slack through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cho, N. Chandramoorthy, K.M. Irick, V. Narayanan, “Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications”, in Journal of Signal Processing Systems Volume 76, Issue 2, Aug. 2014 (First three authors supervised)
Moon Seok Kim, Huichu Liu, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan, “A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter,” IEEE Transactions on Electron and Devices, 6 pages. (First author supervised and second author co-supervised)
Shukla, A. Parihar, E. Freeman, H. Paik, G. Stone, V. Narayanan, H. Wen, Z. Cai, V. Gopalan, R. Engel-Herbert, D. G. Schlom, A. Raychowdhury, and S. Datta “Synchronized charge oscillations in correlated electron systems”, Scientific Reports 4:4964, May 14, 2014.
Pandey, V. Saripalli, J. Kulkarni, S. Datta, V. Narayanan, “Impact of single trap random telegraph noise on heterojunction TFET SRAM stability” in IEEE Electron Device Letters, vol. 35, no. 3, pp. 393–395, Mar. 2014. (Second author co-supervised)
Huichu Liu, Xueqing Li, Ramesh Vaddi, Kaisheng Ma, Suman Datta and Vijaykrishnan Narayanan, “Tunnel FET RF Rectifier Design for Energy Harvesting Application”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2014, (First author co-supervised and next three authors supervised).
Huichu Liu, M. Cotter, S. Datta and V. Narayanan, “Soft Error Performance Evaluation on Emerging Low Power Devices”, IEEE Transactions on Device and Materials Reliability (TDMR), vol.14, no.2, pp.732,741, June 2014. (first author co-supervised, second author supervised)
Suman Datta, Huichu Liu, V. Narayanan, “Tunnel FET Technology: A Reliability Perspective”, Microelectronics Reliability (MR), Vol. 54, Iss. 5, Pages 861–874, May 2014.
Pandey, R. Bijesh, Huichu Liu, V. Narayanan, S. Datta, “Electrical Noise in Heterojunction Interband Tunnel FETs”, IEEE Transactions on Electronic Devices (TED), vol.61, no.2, pp.552,560, Feb. 2014. (Third author co-supervised)
Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan: A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. JETC 9(1): 5 (2013) (Second author supervised)
Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta: Steep-Slope Devices: From Dark to Dim Silicon. IEEE Micro 33(5): 5059 (2013) (First author supervised)
Ahmed Al-Maashri, Matthew Cotter, Nandhini Chandramoorthy, Michael DeBole, Chi-Li Yu, Vijaykrishnan Narayanan, Chaitali Chakrabarti: Hardware Acceleration for Neuromorphic Vision Algorithms. Signal Processing Systems 70(2): 163-175 (2013) (First four authors supervised)
Liu, L., N. Vijaykrishnan, S. Datta. February 2013. A Programmable Ferroelectric Single Electron Transisistor. Applied Physics Letters. Volume 102, Issue 5, 4 pages.
Yang, S., P. Gupta, M. Wolf, D. Serpanos, Y. Xie, N. Vijaykrishnan. September 2012. Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. ACM Transactions on Embedded Computing Systems (TECS). Volume 11, Issue 3, Article 62.
Singh, P. N. Vijaykrishnan, D. Landis. June 2012. Targeted Random Test Generation for Power-aware Multicore Designs. ACM Transactions on Design Automation of Electronic Systems. Volume 17, Number 3, 25 pages.
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. October 2011. Soft Error Modeling and Analysis of the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Phsyics Research A 652(1):370-373.
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. October 2011. Cosmic Ray Background Effects on the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Phsyics Research A 652(1):338-341.
Yu, C.-L., J. S. Kim, L. Deng, S. Kestur*, N. Vijaykrishnan, C. Chakrabarti. July 2011. FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data. Journal of Signal Processing Systems 64(1):109-122. (Fourth author co-supervised by candidate)
Saripalli, V., G. Sun, A. Mishra, Y. Xie, S. Datta and N. Vijaykrishnan. June 2011. Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1(2). (INVITED)
Wang, F. Chen, C. Nicopoulos, X. Wu, Y. Xie, N. Vijaykrishnan. 2011. Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 295-307.
Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu and S. Datta. Feb 2011. Experimental Staggered-Source and N+ Pocket-Doped Channel III-V Tunnel Field-Effect Transistors and Their Scalabilities. Applied Physics Express, Vol. 4, pp. 024105, February 2011
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. 2010. Soft Error Modeling and Analysis of the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Physics Research A. Volume 652(1) p. 370-373
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. 2010. Cosmic Ray Background Effects on the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Phsyics Research A. 652(1), p. 338-341
Yu, C-L, K. Irick*, C. Chakrabarti, V. Narayanan. December 2010. Multidimensional DFT IP Generator for FPGA Platforms. IEEE Transactions on Circuits and Systems. Online at IEEE Explore – Digital Object Identifier 10.1109/TCSI.2010.2078750. (Second author supervised by candidate)
Mishra A.K, A. Yanamandra*, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan and C. Das. December 2010. RAFT: A Router Architecture with Frequency Tuning for On-chip Networks. Journal of Parallel and Distributed Computing. Online at Elsevier Science – Digital Object Identifier:10.1016/j.jpdc.2010.09.005. (Second author co-supervised by candidate)
Saripalli*, V, L. Liu, S. Datta, and V. Narayanan. October 2010. Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits. Journal of Low Power Electronics 6:415-428. (First author co-supervised by candidate)
Nicopoulos*, C. A., S. Srinivasan*, A. Yanamandra*, D. Park, N. Vijaykrishnan, C. R. Das, M. J. Irwin. July-September 2010. On the Effects of Process Variation in Network-on-Chip Architectures. IEEE Transactions on Dependable and Secure Computing (TDSC) 7(3):240-254. (First two authors supervised and third author co-supervised by candidate)
Mookerjea, S., D. Mohata, T. Mayer, N. Vijaykrishnan, S. Datta. June 2010. Temperature-Dependent I-V Characteristics of a Vertical In0.53Ga0.47AS Tunnel FET. IEEE Electron Device Letters 31(6):564-566.
Hung, W-L., Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2010. Total Power Optimization for Combinational Logic Using Genetic Algorithms. Journal of VLSI Signal Processing Systems 58(2):145-160.
Kim*, J. S., P. Mangalagiri*, K. Irick*, M. Kandemir, N. Vijaykrishnan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun. December 2009. An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. IEEE Transactions on Computers 58(12):1654-1667. (First and third authors supervised and second author co-supervised by candidate)
Mookerjea, S., R. Krishnan*, S, Datta, N. Vijaykrishnan. October 2009. On Enhanced Miller Capacitance Effect in Inter-Band Tunnel Transistors. IEEE Electron Device Letters 30(10):1102-1104. (Second author co-supervised by candidate)
Mookerjea, S., R. Krishnan*, S. Datta, N. Vijaykrishnan. September 2009. Effective Output Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation. IEEE Transactions on Electron Devices 56(9):2092-2098. (Second author co-supervised by candidate)
DeBole*, M., R. Krishnan*, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao, N. Vijaykrishnan. August 2009. New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. International Journal of Parallel Programming 37(4):417-431. (First two authors co-supervised by candidate)
Ramanarayanan*, R., V. Degalahal*, R. Krishnan*, J. Kim*, N. Vijaykrishnan, Y. Xie, M. Irwin, K. Unlu. July-September 2009. Modeling Soft Errors at Device and Logic Level for Combinational Circuits. IEEE Transactions on Dependable and Secure Computing (TDSC) 6(3):202-216. (First and third authors co-supervised, second and fourth authors supervised by candidate)
Hu*, J., F. Li, V. Degalahal*, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. July 2009. Compiler-assisted Soft Error Detection under Performance and Energy Constraints in Embedded Systems. ACM Transactions on Embedded Computing Systems 8(4):27.1-27.29. (First and third authors supervised by candidate)
Mutyam*, M., F. Wang, R. Krishnan*, N. Vijaykrishnan, M. Kandemir, Y. Xie, M. J. Irwin. July 2009. Process Variation Aware Adaptive Cache Architecture and Management. IEEE Transactions on Computers 58(7):865-877. (First author supervised and third author co-supervised by candidate)
Eachempati*, S., N. Vijaykrishnan, A. Nieuwoudt, Y. Massoud. April 2009. Predicting the Performance and Reliability of Future Field Programmable Gate Arrays Routing Architectures with Carbon Nanotube Bundle Interconnect. IET Circuits, Devices, & Systems 3(2):64-75. (First author co-supervised by candidate)
Ragheb, T., A. Ricketts*, M. Modal, S. Kirolos, G. Link*, N. Vijaykrishnan, Y. Massoud. February 2009. Design of Thermally Robust Clock Trees using Dynamically Adaptive Clock Buffers. IEEE Transactions on Circuits and Systems (TCAS) 56(2):374-383. (Second and fifth authors supervised by candidate)
Srinivasan*, S., F. Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini. September 2008. Exploring Architectural Solutions for Energy Optimizations in Bus Based SoC. IET Computers & Digital Techniques 2(5):347-354.
Celik, C., K. Unlu, K. Ramakrishnan*, R. Rajaraman*, N. Vijaykrishnan, M. J. Irwin, Y. Xie. August 2008. Thermal Neutron Induced Soft Error Rate Measurement in Semiconductor Memories and Circuits. Journal of Radioanalytical and Nuclear Chemistry 278(2):509-512. (Third author supervised and fourth author co-supervised by candidate)
Gayasen*, A., N. Vijaykrishnan, M. Kandemir, A. Rahman. July 2008. Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Transactions on VLSI 16(7):882-893. (First author co-supervised by candidate)
Yang, S., W. Wang, T. Lu, W. Wolf, N. Vijaykrishnan, Y. Xie. July 2008. Case Study of Reliability-Aware and Low-Power Design. IEEE Transactions on Very Large Scale Integration (VLSI) 16(7):861-873.
Srinivasan*, S., R. Krishnan*, P. Mangalagiri*, Y. Xie, N. Vijaykrishnan, M. J. Irwin, K. Sarpatwari. April-June 2008. Toward Increasing FPGA Lifetime. IEEE Transactions on Dependable and Secure Computing 5(2):115-127. (Third and third authors supervised and second author co-supervised by candidate)
Tsai*, Y., F. Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin. April 2008. Design Space Exploration for Three-Dimensional Cache. IEEE Transactions on VLSI 16(4):444-455. (First author supervised by candidate)
Brooks, R., P. Govindaraju, M. Pirretti*, N. Vijaykrishnan, M. Kandemir. November 2007. On the Detection of Clones in Sensor Networks Using Random Key Predistribution. IEEE Transactions on Systems, Man, and Cybernetics 37(6):1246-1258. (Third author supervised by candidate)
Xie, Y., L. Li*, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. October 2007. Reliability-Aware Co-synthesis for Embedded Systems. Journal of VLSI Signal Processing 49(1):87-99. (Second author supervised by candidate)
Wang, F., M. Debole*, X. Wu, Y. Xie, N. Vijaykrishnan, M. J. Irwin. September 2007. On-chip Bus Thermal Analysis and Optimization. IET Computer & Digital Techniques 1(5):590-599. (Second author co-supervised by candidate)
Kim*, S., N. Vijaykrishnan, M. J. Irwin. August 2007. Reducing Non-Deterministic Loads in Low-Power Caches via Early Cache Set Resolution. Microprocessors and Microsystems 31(5):293-301. (First author supervised by candidate)
Hu*, J., N. Vijaykrishnan, M. J. Irwin, M. Kandemir. July 2007. Optimizing Power Efficiency in Trace Cache Fetch Unit. IET Computers and Digital Techniques 1(4):334-348. (First author supervised by candidate)
Gayasen*, S. Srinivasan*, N. Vijaykrishnan, M. Kandemir. 2007. Design of Power-Aware FPGA Fabrics. International Journal of Embedded Systems 3(1/2):52-64. (First author co-supervised and second author supervised by candidate)
Pirretti*, M., S. Zhu, N. Vijaykrishnan, P. McDaniel, M. Kandemir, R. Brooks. September 2006. The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense. International Journal of Distributed Sensor Networks 2(3):267-287. (First author supervised by candidate)
T., J. Rubio, L. K. John, A. Sivasubramaniam, N. Vijaykrishnan. January 2007. OS-aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems. IEEE Transactions on Computers 56(1):2-17.
Lee*, J., N. Vijaykrishnan, M. J. Irwin. July 2006. Block-Based Frequency Scalable Technique for Efficient Hierarchical Coding. IEEE Transactions on Signal Processing 54(7):2559-2566. (First author co-supervised by candidate)
Lee*, J., N. Vijaykrishnan, M. J. Irwin. May 2006. Efficient VLSI Implementation of Inverse Discrete Cosine Transform. IEEE Transactions on Circuits and Systems for Video Technology 16(5):655-662. (First author co-supervised by candidate)
Lee*, J., N. Vijaykrishnan, M. J. Irwin, W. Wolf. February 2006. An Efficient Architecture for Motion Estimation and Compensation in the Transform Domain. IEEE Transactions on Circuits and Systems for Video Technology 16(2):191-201. (First author co-supervised by candidate)
Zhang, W., Y-F Tsai*, D. Duarte, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2006 Reducing Dynamic and Leakage energy in VLIW Architectures. ACM Transactions on Embedded Computing Systems 5(1):1-28. (Second author supervised by candidate)
Vijaykrishnan, N., Xie, Y. January 2006. Reliability concerns in embedded system designs. IEEE Computer. 39(1):118-120. (Invited) (Principal author)
Swankowski, E., N. Vijaykrishnan, R. Brooks, M. Kandemir, M. J. Irwin. Symmetric Encryption in Reconfigurable and Custom Hardware. International Journal of Embedded Systems 1(3/4):205-217. (First author supervised by candidate)
Lattanzi, E, A. Gayasen, M. Kandemir, N. Vijaykrishnan, L. Benini, A. Bogliolo. 2005 Improving Java performance using dynamic method migration on FPGAs. International Journal of Embedded Systems 1(3/4):228-236. (First author supervised and second author co-supervised by candidate)
Hu, J. S., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. November 2005. Analyzing Data Reuse for Cache Reconfiguration. ACM Transactions on Embedded Computing Systems 4(4):851-876. (First author supervised by candidate)
Kadayif, I., M. Kandemir, G. Chen, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam. November 2005. Compiler-directed High-level Energy Estimation and Optimization. ACM Transactions on Embedded Computing Systems (TECS) 4(4):819-850.
Degalahal, V., L. Li, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. October 2005. Soft Error Issues in Low Power Caches. IEEE Transactions on VLSI 13(10):1157-1166. (First author supervised and second author co-supervised by candidate)
Murali, S., T. Theocharides, N. Vijaykrishnan, M. J. Irwin, L. Benini, G. DeMicheli. September-October 2005. Analysis of Error Recovery Schemes for Networks-On-Chips. IEEE Design and Test of Computers, Special Issue on Networks on Chips 22(5):434-442. (Second author co-supervised by candidate)
Kim, S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. July 2005. Exploiting Temporal Loads for Low Latency and High Bandwidth Memory. IEE Proceeding: Computers and Digital Techniques 152(4):457-455. (First author supervised by candidate)
Kim, E-J. G. Link, K. H. Yum, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, C. R. Das. June 2005. A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. IEEE Transactions on Computers 54(6):660-671. (Second author supervised by candidate)
Yang, S., W. Wolf, N. Vijaykrishnan. June 2005. Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. IEEE Transactions on Computers 54(6):714-726. (25% contribution)
Zhang, W., Y-F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, V. De. March 2005. Leakage-Aware Compilation for VLIW Architectures. IEE Proceedings: Computers and Digital Techniques 152(2):251-260. (Second author co-supervised by candidate) (Invited) (Equal contributions)
Kadayif, I., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. March 2005. An Integar Linear Programming Based Tool for Wireless Sensor Networks. Journal of Parallel and Distributed Computing (JPDC) 65(3):247-260. (20% contribution)
Kim, S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. March 2005. Optimizing Leakage Energy Consumption in Cache Bitlines. Journal of Design Automation for Embedded Systems (DAEM) 9(1):5-18. (First author supervised by candidate)
Tsai, Y-F., D. Duarte, N. Vijaykrishnan, M. J. Irwin. November 2004. Characterization and Modeling of Run-Time Techniques for Leakage Power Reduction. IEEE Transactions on Very Large Scale Integration Systems 12(11):1221-1233. (First author co-supervised by candidate)
Chen, G., B. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, R. Chandramouli. September 2004. Studying Energy Tradeoffs in Off-loading Computation/Compilation in Java-enabled Mobile Devices. IEEE Transactions on Parallel and Distributed Systems (TPDS) 15(9):795-809. (Second author co-supervised by candidate)
Parikh, A., S. Kim, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. May 2004. Instruction Scheduling for Low Power. Journal of VLSI Signal Processing Systems 37(1):129-149. (Second author supervised by candidate) (Equal contributions by authors)
Zhang, W., J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. March 2004. Reducing Instruction Cache Energy Consumption Using a Compiler-based Strategy. ACM Transactions on Architecture Code Optimization (TACO) 1(1):3-33. (Second and third authors supervised by candidate)
Juran, J., A. R. Hurson, N. Vijaykrishnan, S. Kim. March 2004. Data Organization and Retrieval on Parallel Air Channels. ACM/Kluwer Wireless Networks (WINET) Journal 10(2):183-195. (Contributing author)
Kandemir, M., J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, A. Parikh. February 2004. A Compiler Based Approach for Dynamically Managing Scratch-pad Memories in Embedded Systems. IEEE Transactions on Computer Aided Design 23(2):243-260. (Contributing author)
Kim, S., S. Tomar, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. January 2004. Energy-Efficient Java Execution Using Local Memory and Object Co-location. IEE Proceedings: Computers and Digital Techniques 151(1):33-42. (First two authors supervised by candidate)
Kim, N., T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, N. Vijaykrishnan. December 2003. Leakage Current: Moore’s Law Meets Static Power. IEEE Computer, Special Issue on Power- and Temperature-Aware Computing 36(12):68-75. (Equal contributions by authors) (Sixth author supervised by candidate)
Saputra, H., N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, W. Zhang. September 2003. Masking the Energy Behavior of Encryption Algorithms. IEE Proceedings: Computers and Digital Techniques 150(5):274-284. (First author co-supervised by candidate – 30% contribution) (Invited among best papers at DATE 2003).
Kim, S., N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin. May 2003. Partitioned Instruction Cache Architecture for Energy Efficiency. ACM Transactions on Embedded Computing Systems: Special Issue on Compilers, Architecture, and Synthesis for Embedded Systems 2(2):163-185. (First author supervised by candidate) (Selected among best papers from CASES 2001)
Li, L, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, A. Sivasubramaniam. February 2003. Managing Leakage Energy in Cache Hierarchies. Journal of Instruction-level Parallelism, Volume 5. (First and third authors co-supervised by candidate) (Invited among best papers presented at PACT 2002)
Vijaykrishnan, N., M. Kandemir, M. J. Irwin, H. Kim, W. Ye. January 2003. Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. IEEE Transactions on Computers 52(1):59-76. (Equal contributions by authors) (Fourth author supervised by candidate)
Duarte, D., N. Vijaykrishnan, M. J. Irwin. December 2002. A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations. IEEE Transactions on VLSI 10(6):844-855. (30% contribution) (IEEE CAS Transactions on VLSI Best Paper Award)
An, N., S. Gurumurthi, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. December 2002. Energy-Performance Trade-Offs for Spatial Access Methods on Memory-Resident Data. International Journal on Very Large Databases 11(3):179-197. (Contributing author) (Invited among best papers presented at VLDB; 5 out of the 59 papers presented at VLDB were selected)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin and M. Wolczko. November 2002. Tuning Garbage Collection for Reducing Memory System Energy in an Embedded Java Environment. ACM Transactions on Embedded Computer Systems 1(1):27-55. (Equal contributions by authors)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Wolf. October 2002. Using Memory Compression for Energy Reduction in an Embedded Java System. Journal of Circuits, Systems and Computers 11(5):537-556. (Equal contributions by authors)
Kandemir, M., N. Vijaykrishnan, M. J. Irwin, W. Ye. December 2001. Influence of Compiler Optimizations on System Power. IEEE Transactions on VLSI Systems 9(6):801-804. (Equal contributions by authors)
De La Luz, V., M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin. November 2001. Hardware and Software Techniques for Controlling DRAM Power Modes. IEEE Transactions on Computers, Special Issue on Advances in High Performance Memory Systems 50(11):1154-1173. (Equal contributions by authors)
Radhakrishnan, R., N. Vijaykrishnan, L. K. John, A. Sivasubramaniam, J. Rubio, J. Sabarinathan. February 2001. Java Runtime Systems: Characterization and Architectural Implications. IEEE Transactions on Computers. 50(2):131-146. (40% contribution)
Esakkimuthu, G., H. S. Kim, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. February 2001. Investigating Memory System Energy Behavior Using Software and Hardware Optimizations. Special Issue in Low Power System Design of VLSI DESIGN. 12(2):151-165. (First/second author supervised by candidate)
Bishop, B., V. Lyuboslavsky, N. Vijaykrishnan, M. J. Irwin. February 2001. Design Considerations for Databus Charge Recovery. IEEE Transactions on Very Large Scale Integration Systems 9(1):104-106.(Second author supervised).
Vijaykrishnan, N., N. Ranganathan. November 2000. Supporting Object Accesses in a Java Processor. Proceedings of IEE – Computers and Digital Techniques Journal 147(6):435-443. (Principal author)
Chandramouli, R., N. Vijaykrishnan, N. Ranganathan. December 1998. Sequential Tests for Integrated Circuit Failure Analysis. IEEE Transactions on Reliability 47(4):463-471. (Equal contributions by authors)
Ranganathan, N., N. Vijaykrishnan, N. Bhavanishankar. August 1998. A Linear Array Processor with Dynamic frequency Clocking for Image Processing Applications. IEEE Transactions on Circuits and Systems for Video Technology. 8(4):435-445. (50% contribution)

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