Optimal Placement of Cores, Caches and Memory Controllers in Network On-Chip

Abstract: Parallel programming is emerging fast and intensive applications need more resources, so there is a huge demand for on-chip multiprocessors. Accessing L1 caches beside the cores are the fastest after registers but the size of private caches cannot increase because of design, cost and technology limits. Then split I-cache and D-cache are used with […]

Publications

Discovering Triangles in Portraits for Supporting Photographic Creation, S He, Z Zhou, F Farhat, JZ Wang, IEEE Transactions on Multimedia, Aug 2017. Intelligent Portrait Composition Assistance — Integrating Deep-learned Models and Photography Idea Retrieval, F Farhat, MM Kamani, S Mishra, JZ Wang, July 2017. Skeleton Matching with Applications in Severe Weather Detection, MM Kamani, F […]

EECS PSU

Farshid Farhat @ EECS PSU PhD Candidate School of Electrical Engineering and Computer Science The Pennsylvania State University Address: 310 IST Building, University Park, PA, 16802. Email: fuf111 AT psu DOT edu Web: Farshid Farhat ‘s Site@PSU About Me I am a member of Intelligent Information Systems (IIS) research lab at Penn State. I am working with Prof. […]