5 Stage Pipelined CPU – Daniel Trainor’s Professional Site

The 5 Stage Pipelined CPU can run as many as five instructions at once. Each instruction gets completed through five individual stages: Instruction Fetch, Instruction Decode, Execution, Memory, and Writeback.

This was a semester-long project within my CMPEN 331 Computer Organization and Design course to build a 5 Stage Pipelined CPU in Verilog.

Diagram of Five Stage Pipelined CPU

In the IF stage, there is an instruction memory module and an adder between two
pipeline registers. The leftmost pipeline register is the PC; it holds 100. At the end of the first cycle (at the rising edge of clk), the instruction fetched from instruction memory is written into the IF/ID register. Meanwhile, the
output of the adder (PC + 4, the next PC) is written into PC.

The instruction in the ID stage comes from the IF/ID register. Two operands are read from the register file (Regfile in the figure) based on rs and rt, although the lw instruction does not use the operand in the register rt. The immediate (imm) is sign-extended into 32 bits. The regrt signal is used in the ID stage that selects the destination register number; all others must be written into the ID/EXE register for later use. At the end of the second cycle, all the data and control signals, except for regrt, in the ID stage are written into the ID/EXE register. At the same time, the PC and the IF/ID register are also updated.

In the EXE stage, the ALU performs addition, and the multiplexer selects the immediate. A letter “e” is prefixed to each control signal in order to distinguish it from that in the ID stage. The EXE/MEM register is updated at the end of the cycle.

The only task in the MEM stage is to read data memory. All the control signals have the prefix “m”. The MEM/WB pipeline registers are updated at the end of the cycle.

In the WB stage, the memory data is selected and will be written into the register file at the end of the cycle. All the control signal have a prefix “w”. Finally, the destination register is updated.

In each of the forthcoming clock cycles, an instruction will be committed and a new instruction will enter the pipeline. At its most efficient state, there can be as many as five instructions running at once within the pipelined CPU.