PREVIOUS: Dynamic Storage Allocator
The Mini CPU uses Verilog Code to simulate a 5-stage pipelined CPU with internal forwarding. The stages include Instruction Fetch, Instruction Decode, Execution, Memory Access, and Write Back, all of which are developed in several individual laboratory sessions over the course of the semester. The designs are based on the course textbook as well as additional instructor-provided laboratory documents. In addition to the Verilog Code, which includes the Verilog Design and Testbench, basic simulations of waveforms were performed for basic verification purposes. The report document for this project is featured below:
This project represents the first instance where students are exposed to coding related to hardware. Creating the Mini CPU provides a basic foundation for the hardware aspect of computers. In order to move towards the goal of working with computers in entertainment, it requires a taste of both hardware and software.