Five-stage pipelined CPU for Field Programmable Gate Arrays

Using Xilinx, created a CPU in a MIPs assembly language with Instruction Fetch, Instruction Decode, Execution, Memory Access, and Write Back stages designed to pipeline such that a new instruction is entered every cycle to maximize efficiency of the CPU. The CPU is able to thus run instructions such as mathematical operations and memory reading…Continue Reading Five-stage pipelined CPU for Field Programmable Gate Arrays

Replication of Penn State LionPath Courses and Finances System

Created a set of classes in Python to replicate PSU’s course scheduling and financial management system. Included simulating course registration from a catalog, packaging courses into a semester, managing Student Accounts and Staff Accounts from implementation of a Person class, and handling loan and financial payments with such accounts. GitHub: https://github.com/hersh-b/Penn-State-Courses-and-Finances-System…Continue Reading Replication of Penn State LionPath Courses and Finances System