PROJECTS

5 Stage Pipelined Mini CPU (Skills: Xilinx, Verilog) 05/2022

 Built a 5-stage pipelined CPU which simulated fetch, decode, execute, memory, writeback functions of CPU.
 Enhanced the speed of CPU using processor pipelining that helped minimize memory and branch delays.
 Analyzed the schematics, floor planning, IO planning, bit stream, data path and simulation waveforms at various stages of CPU creation.

 Implemented data storage architecture containing multiple disks inside a single storage enclosure.
 Created utility used to manage & monitor RAID devices with read, write, test, cache and networkingfunctionalities.
 Integrated numerous disks into existing storage systems, configured 16 disks of size 64kb as a single 1MBdisk.
 Admin
istered various functionality such as mount, unmount, read, write, seek to disk, seek to block.

 Implemented object-oriented programming to create a database system that holds all properties listed by a
real estate brokerage firm.
 Designed a database using Apache Derby in Java and created a Graphical User Interface using NetBeans
 Added various functions such as sort, search, add, update and delete record based on user requirement that enhanced the efficiency and usability of the system.
 Implemented statistical functionalities to model out the mean, median and standard deviation of properties listed based on the area it is located in.