Ultra Low Power Electronics
Ever since the inception of metal oxide semiconductor field effect transistor (MOSFET), Scaling has been the primary driving force behind its unprecedented success. The early era of scaling (~1975-2005: Dennard Scaling) had two characteristic features: dimension scaling which allowed the number of transistor per chip to increase by 1000000x and consequently their speed to increase by 1000x, and voltage scaling which kept the power density practically constant throughout this scaling regime. However, around 2005, the voltage scaling almost stopped as further reduction in the supply voltage (VDD) and hence the threshold voltage (VTH) was leading to exponential increase in the OFF state current (IOFF). This is a direct consequence of non-scalability of the subthreshold swing (SS) to below 60mV/decade arising out of Boltzmann statistics that governs the operation of conventional MOSFETs. Dimension scaling, however, continued beyond 2005, but, under the new generalized scaling rules. This inevitably led to increase in the power density at the same rate as the integration density. The actual scenario is made worse by non-scaling factors which escalated static and leakage power densities at a much faster rate. Power/heat dissipation, henceforth, became the main problem for high performance microprocessors. Today, in 2016, even dimension scaling seems extremely challenging beyond 10nm gate length (LG) owing to fundamental material limitations. So it is not too far when all aspects of MOSFET scaling will completely stop, marking the end of the silicon complementary metal oxide semiconductor (CMOS) era. Therefore, in order to restore the golden era of transistor scaling, energy efficient and high performance innovative device ideas based on aggressively scalable novel materials need to be conceived on an urgent and immediate basis.
From the above discussion it is obvious that post-Si-CMOS devices have to resolve two key challenges: length scaling and voltage scaling. For length scaling, low dimensional systems like nanotubes, nanowires and very recently nanosheets are being considered as alternative materials to Si due to their inherent electrostatic integrity that allows fundamentally superior scaling properties. Voltage scaling, however, necessitates steep slope devices which in turn require operation beyond Boltzmann statistics. Several steep switching device concepts like tunneling FETs, negative capacitance ferroelectric FETs, excitonic FETs and spin-based FETs have been proposed. Remeber that the objective for post-Si device design, is mainly two-fold: SS slope should be as abrupt as possible (ideally zero) to meet the low power requirement and ON current should be as high as possible to increase the device speed.
Devices for Internet of Things (IoT)
Low Power, High Speed, Flexible Devices are essential for the success of the emerging technology called IoT. Experts estimate that the IoT will consist of almost 50 billion objects by 2020.
Contact Engineering for 2D Materials
Two dimensional (2D) materials like graphene, black phosphorus, various transition metal dichalcogenides (TMDs) like MoS2, WSe2 and beyond are drawing significant attention as promising candidates for future electronic and optoelectronic devices which include logic transistors, radio frequency (RF) devices, light emitting diodes, solar cells and sensors of all types: chemical, biological, mechanical and thermal. The experimental results from first generation prototype 2D-devices show compelling evidence for high performance. However, as we move on to the second generation of 2D devices and start to shrink the device dimensions in order to further increase the performance (ON current, speed, sensitivity etc.), we run into fundamental scaling problems arising due to the contacts. Contact resistance is one of the major factors which could potentially limit the performance of aggressively scaled devices based on two-dimensional (2D) materials . It is now widely accepted that metal-2D contacts are mostly characterized by Schottky barriers. Hence, various contact engineering strategies have been adopted to minimize the Schottky barrier height at the metal-2D interface and thereby reduce the contact resistance. These includes work function engineering, interface engineering and phase engineering among others.
At the same time emphasis need to be given to study the scalability of metal-2D contacts due to the fact that in an aggressively scaled device both channel length (LCH) and contact length (LC) have to be reduced by similar factor. While length scaling reduces the channel resistance (RCH) it also increases the contact resistance (RC) leading to a non-monotonic total resistance (RTOTAL) which ultimately limits the device scaling. In this context it is to be reminded that such non-scalability of total resistance ultimately limited the implementation of carbon nanotubes (CNTs) into integrated circuits in spite of CNTs being the most promising material for post silicon complementary metal oxide semiconductor (CMOS) technology. IBM researchers were able to scale the channel length of CNT field effect transistors (FETs) to sub-10nm regime; however, the contact lengths for such CNT-FETs could not be scaled beyond 200nm since contact resistance started to dominate the device performance. Therefore, it is important and timely to determine the ultimate scalability of contacts to 2D materials at an early stage since these are also being considered as alternative materials for future electronic and optoelectronic devices. One possible advantage that the 2D materials might have over CNTs is that the 2D materials have one more degree of dimensionality. From a simple qualitative mode mis-match argument, it is easier to couple a three dimensional (3D) contact to a two-dimensional (2D) nanosheet than it is to a one-dimensional (1D) nanotube or nanowire. Note that the mode mis-match is responsible for carriers back scattering at a metal-semiconductor contact interface and ultimately give rise to a finite contact resistance.
Electrochemical Synthesis of 2D Materials
Materials that are only one layer thick have really excited scientists across different disciplines ever since the discovery of graphene. These so called two dimensional (2D) materials demonstrate unique physical properties like room temperature quantum Hall effect, charge density waves, high temperature superconductivity and high carrier mobility owing to their atomically thin nature. In fact the fascinating aspects of 2D materials are realized when the thickness is reduced to monolayer. Chemical vapor deposition (CVD) is the most widely used technique to obtain large area 2D-monolayers. However, the success of CVD is dependent on availability of precursor materials and process conditions like temperature, pressure, air flow etc. Also the CVD grown samples suffers from polycrystallinity and non-uniform thicknesses which limit the quality of the samples. So far the best quality samples of 2D materials are obtained with micromechanical exfoliation from naturally occurring single crystals. The Nobel Prize was awarded in 2010 for the synthesis of graphene using this technique. The exfoliation process, however, gives randomly distributed flakes of different thicknesses ranging from mono-layers (~0.6nm) to few layers (~50-100nm). The lateral dimensions of the flakes are also limited to only few micrometers. Also, the probabilities of getting thinner layers are quite low and uncontrollable. In the above context, our research on an unique electrochemical technique could provide a breakthrough solution since this process is energy efficient, ultra-fast, and cost effective and at the same time provides almost 100% yield of monolayers of 2D materials with 100x larger area.