The second Young Architect Workshop (YArch ’20, pronounced “why arch”) will provide a forum for junior graduate students studying computer architecture and related fields to present early stage or on-going work and receive constructive feedback from experts in the field as well as from their peers. Students will also receive mentoring opportunities in the form of keynote talks, a panel discussion geared toward grooming young architects, and 1-on-1 meetings with established architects.

Students will receive feedback from experts both about their research topic in general and more specifically, their research directions. Students will also have an opportunity to receive valuable career advice from leaders in the field and to network with their peers and develop long-lasting, community-wide relationships.


The central theme of this workshop is to serve as a welcoming venue for junior graduate students to present their ongoing work and receive feedback from experts within the community. In addition, this workshop also aims to help early-stage graduate students in building connections both with their peers and established architects in the community. To this end, YArch will include:

Route to Top-tier: Each submitted work will receive two or more expert reviews. The aim of these reviews will be to give early guidance on important boxes to check for the submitted work to be a future successful top tier conference paper.

Meet an Architect: As part of the workshop, attendees will be paired with experts in their chosen research area to get feedback on their ongoing work and future research directions.

Becoming an Architect: The workshop will include keynote talks from academic and industry leaders specifically geared towards early stage graduate students.

Ask an Architect: The workshop will include a panel of established architects in industry and academia from whom students can seek career advice.


YArch strives to be an inclusive and diverse venue for Young Architects and below are some statistics to show how we performed along this dimension at YArch’19. Future versions for YArch will strive to improve in this regard.

– Five out of ten accepted student submissions were from female students.
– Of the two keynote speakers, one is from industry and one from academia, including one female speaker.
– Of the five panelists, three are from industry and two from academia, including two female panelists.
– Of the two workshop organizers,  one is from industry and one from academia, including one female organizer.
– Of the twenty nine PC members, nine are from industry and twenty from academia, including six female members.

Travel support

YArch is committed to providing significant travel support to students accepted at the workshop. We will strive to cover the full cost of attendance for workshop participants. A couple of other clarifications:

– Students accepted to YArch through our submission will be eligible for YArch travel grants and these travel grants will be processed after YArch acceptance notifications are sent out. These are separate from ASPLOS conference travel grants, however, students would receive at most one of the two kinds of travel grants.
– Given our current levels of sponsorship, we expect YArch travel grants to be over 1,000 USD. We are working to raise more sponsorships.
– While issuing YArch travel grants, students without prior first author ISCA/MICRO/ASPLOS/HPCA papers will be prioritized.


Eligibility: Applicants must be graduate students (Ph.D or Masters) in computer architecture and related fields who have completed less than 3 years of graduate school (Masters and/or PhD) at the time of the workshop. A note from the student’s research advisor attesting this is required as part of the submission.

Call for Submissions: Eligible students are invited to submit their early stage or on-going work to this workshop. Submitted work should not have been presented as part of a prior ACM/IEEE conference.

The workshop invites papers from all areas of computer architecture, broadly defined. Topics of interest include, but not limited to:
– Datacenter systems
– Hardware acceleration
– Memory hierarchy
– Virtualization
– Security
– Microarchitecture
– GPUs
– Parallel architectures
– Emerging technologies

Note: This workshop is not a venue for publication and there will be no formal proceedings.

Submission guidelines: The goal of this workshop is to help students think about a problem/idea in an holistic manner and communicate your ideas to the wider community, so that we can provide some valuable early-stage feedback. To this end, we encourage you to cover the following aspects in your submission:

Scope of problem/idea: Provide clear context for and scope of the problem(s) or idea(s) you intend to work on. This will likely form the basis of the introduction/background sections of your future work(s).

Solution: Provide an overview of the design and implementation aspects of your solution(s) to the problem(s) described above. Given this is on-going work, focus more on providing breadth than depth. For example, beside describing the design of your idea, enlist the various system aspects which your proposed solutions will affect (e.g. does your proposed solution affect coherence protocols?) and that if you plan to discuss these effects in your future submission(s).

Evaluation methodology: Discuss the evaluation methodology you plan to adopt to test the efficacy of your ideas. For example, the workloads that you plan to use, the tools you’ll employ (e.g., architectural simulator, real world experiments, FPGA prototypes), etc.

Related work: This can be the traditional related work section. Please specify if you plan to quantitatively compare against some prior work. 

Submission details
– Submissions must be PDF files, in 2-column, single-spaced, 10pt format.
– Submissions must be at most 2 pages long, not including references.
Submissions are double-blind. Please do not have any author identifying information in the paper submitted.
– Please have your research advisor send the workshop organizers an email with the following subject line “<Your name> meets YArch’20 eligibility requirements” to “yarch.asplos20@gmail.com”.
– Submission site: Link
– Submission deadline: January 24th 2020 (Friday), 11:59pm (Pacific)

Declaring conflicts: When registering a submission, all its co-authors must provide information about conflicts with the YArch ’20 program committee members. You are conflicted with a member if: (1) you are currently employed at the same institution, have been previously employed at the same institution within the past two years (2016 or later), or are going to begin employment at the same institution; (2) you have a past or present association as thesis advisor or advisee (no time limit); (3) you have collaborated on a project, publication, grant proposal, or editorship within the past two years (2016 or later); or (4) you have spouse or first-degree relative relations.




Shaizeen Aga, AMD Research

Aasheesh Kolli, Pennsylvania State University

Alexandros Daglis, Georgia Tech.


Mohammad Shahrad, Princeton University

Akshitha Sriraman, University of Michigan

Program Committee:

John Alsop, AMD Research
Arkaprava Basu, Indian Institute of Science, Bangalore
Rangeen Basu Roy Chowdhury, Intel
Jason Clemons, NVidia
Joseph Devietti, University of Pennsylvania
Christopher Fletcher, University of Illinois Urbana-Champaign
Shrikanth Ganapathy, AMD Research
Jayneel Gandhi, VMWare
Suagata Ghose, Carnegie Mellon University
Boris Grot, University of Edinburgh
Akanksha Jain, University of Texas at Austin
Nuwan Jayasena, AMD Research
Onur Kayiran, AMD Research
Samira Khan, University of Virginia
Vincent T. Lee, Facebook
Andrew Lukefahr, Indiana University
Divya Mahajan, Microsoft Research
Prashant Nair, University of British Columbia
Tony Nowatzki, UCLA
Gokul Subramanian Ravi,  University of Wisconsin-Madison
Brandon Reagen, NYU/Facebook
Adrian Sampson, Cornell
Joshua San Miguel, University of Wisconsin-Madison
Abhayendra Singh, Google LLC
Akshitha Sriraman, University of Michigan/ Facebook/ Harvard
Swamit Tannu, Georgia Institute of Technology
Ashish Venkat, University of Virginia
Radha Venkatagiri, University of Illinois Urbana-Champaign
Vivek V Menon, University of Southern California-Information Sciences Institute
Rujia Wang, Illinois Institute of Technology
Daniel Wong, University of California, Riverside
Mengjia Yan, MIT
Jishen Zhao, University of California, San Diego
Yuhao Zhu, University of Rochester