The second Young Architect Workshop (YArch ’20, pronounced “why arch”) will provide a forum for junior graduate students studying computer architecture and related fields to present early stage or on-going work and receive constructive feedback from experts in the field as well as from their peers. Students will also receive mentoring opportunities in the form of keynote talks, a panel discussion geared toward grooming young architects, and 1-on-1 meetings with established architects.

Students will receive feedback from experts both about their research topic in general and more specifically, their research directions. Students will also have an opportunity to receive valuable career advice from leaders in the field and to network with their peers and develop long-lasting, community-wide relationships.

COVID-19 Update

We are extremely disappointed that YArch (along with ASPLOS) has been cancelled this year. Given the situation with COVID-19, it was the right thing to do. However, we are planning to conduct the workshop in a distributed fashion. After careful consideration, here is our plan:

Student Presentations:

– Students presenting at the workshop will be required to upload a 10min video of their presentation to Youtube by March 16th, 2020.
Student presentation playlist: https://www.youtube.com/playlist?list=PLe9IED-JzOQRA-C2Tr9RQsODmD_2rtCZ3
– Viewers may leave questions for the students as comments on their video until March 20th, 2020.
– Students are expected to answer these questions by March 24th, 2020.

Keynotes and Panel:

– We are working towards organizing the keynotes and panels as a webinar.
– Viewers will be able to pose questions to the speakers via a “chat” features.

Keynote-1: Ph.D. Student Advice from a 1980s Ph.D. Student by Prof. Mark Hill (Slides)
Time: March 17th, 2020 (Tuesday), 11am-Noon (US Eastern)
– Video Recording: https://youtu.be/eabxuh3RZNs

Keynote-2: A Research Mindset by Dr. Kathryn McKinley (Slides)
Time: March 17th, 2020 (Tuesday), Noon-1pm (US Eastern)
– Video Recording: https://youtu.be/LJFBm9787cs

Panel: Demystifying Grad School
Panelists: Boris Grot (Univ. of Edinburgh),  Gabriel Loh (AMD Research),  Gilles Pokam (Intel), and Akshitha Sriraman (Univ. of Michigan)
Time: March 19th, 2020 (Thursday), 11am-12:30pm (US Eastern)
– Video Recording: https://youtu.be/mcjXMsyj5DA

1:1 Student Mentoring Sessions:

– We will pair up individual students with senior architects from the community.
– The students and their mentors are encouraged to setup 30min video chats as per their mutual convenience.
– We encourage the students and mentors to conduct these meetings between March 23rd, 2020 (Monday) to March 27th, 2020 (Friday)

Student Poster session has been CANCELLED.


YArch video playlist: https://www.youtube.com/playlist?list=PLe9IED-JzOQRA-C2Tr9RQsODmD_2rtCZ3

This is a tentative program (local times).

8:15 – 8:30am | Opening remarks

8:30 – 9:30am | Keynote – 1

Ph.D. Student Advice from a 1980s Ph.D. Student
Mark Hill (Univ. of Wisconsin)

9:30 – 10:00am | Student presentations – 1

RTL Implementation of a Composable Branch Predictor for Superscalar Out-of-Order Cores
Jerry Zhao (Univ. of California, Berkeley)

Speculation-Free Out-of-Order Commit
Ali Haijiabadi (National Univ. of Singapore)

10:00-10:30am | Break

10:30am – 12:30pm | Student presentations – 2

Approaching a High-Performance, General-Purpose Multi-Threaded Sampling Methodology
Alen Kandathumthodukayil Sabu (National Univ. of Singapore)

Privacy-Preserving Data Types for Secure Cloud Computing
Lauren Biernacki (Univ. of Michigan)

A Hardware Study on Hyperspectral Image Processing
Agreen Ahmadi (Univ. of Michigan)

Cost-Effective Instruction TLB Prefetching
Georgios Vavouliotis (Barcelona Supercomputing Centre)

Automatic and Speculative Parallel-Stage Decoupled Software Pipelining
Zujun Tan (Princeton Univ.)

PMSwitch: Extending Persistence to The Network
Korakit Seemakhupt (Univ. of Virginia)

Efficiently Mapping Applications To Heterogeneous Systems
Hiwot Kassa (Univ. of Michigan)

Enumerating Hardware–Software Splits with Program Rewriting
Gus Henry Smith (Univ. of Washington)

12:30-2:00pm | Lunch

2:00-3:00pm | Keynote – 2

A Research Mindset
Dr. Kathryn McKinley (Google)

3:00-4:00pm | Student presentations – 3

Making Accelerators First-Class Citizens in the Datacenter
Kaitie Lim (Univ. of Washington)

Enabling ORAM on Non-Volatile Main Memories
Yi Zhang (Pennsylvania State Univ.)

Integrated Memory Speculation Framework
Jinho Lee (National Univ. of Singapore)

Smart Priority Assignment in Datacenter Networks
M. R. Siavash Katebzadeh (Univ. of Edinburgh)

4:00-4:15pm | Break

4:15 – 5:45pm | Panel

Demystifying Grad School
Anastasia Ailamaki (EPFL), Irina Calciu (VMware Research), Boris Grot (Univ. of Edinburgh),  Gabriel Loh (AMD Research),  Gilles Pokam (Intel), and Akshitha Sriraman (Univ. of Michigan) 

5:45 – 6:00pm | Closing remarks

TBD – Student poster session (co-located with the conference)


Keynote-1: Ph.D. Student Advice from a 1980s Ph.D. Student (Slides, Video)

Speaker: Mark Hill (Univ. of Wisconsin)

Abstract: “The more things change; the more they stay the same” [Alphonse Karr, 1848]. This talk presents some timeless fundamentals for being a successful graduate student with an emphasis on doing impactful research and managing your advisor.

Bio: Mark D. Hill  is John P. Morgridge Professor and Gene M. Amdahl Professor of Computer Sciences at the University of Wisconsin-Madison, where he also has a courtesy appointment in Electrical and Computer Engineering. His research interests include parallel-computer system design, memory system design, and computer simulation. He received the 2019 Eckert-Mauchly Award and is a fellow of IEEE and the ACM. He serves as Chair of the Computer Community Consortium (2018-19) and served as Wisconsin Computer Sciences Department Chair 2014-2017. Hill has a PhD in computer science from the University of California, Berkeley.

Time: March 17th, 2020 (Tuesday), 11am-Noon (US Eastern)

Keynote-2: A Research Mindset (Slides, Video)

Speaker: Dr. Kathryn McKinley (Google)

Abstract: This session will explore how you handle adversity, your biases about your own abilities and those of others, and give you some practical suggestions for improving your ability to overcome obstacles, innovate in research, and find deeper satisfaction in your work. The session will include individual and group exercises.

Please prepare by writing down your feelings and actions during the period when (1) you submit a paper, it is accepted, submitting the final version, and you present it; and (2) when you submit a paper, it is rejected, and then you resubmit it at least 1 month later.  If you have not had these experiences, write about some other accepting and/or rejecting event (such as getting in or being rejected from graduate school) that requires actions that span at least a few weeks.

Bio: Kathryn S. McKinley is a Senior Staff Research Scientist at Google (2017-present). She received her BA, MS, and PhD from Rice University. Her research interests span programming languages, compilers, runtime systems, operating systems, cloud systems, and architecture with a focus on performance, parallelism, and memory systems. She and her collaborators have produced software systems widely used in industry and academia: the DaCapo Java Benchmarks (31,800+ downloads), the TRIPS Compiler, the Hoard memory manager (used by OS X), the MMTk memory management toolkit, the Immix garbage collector (used by Jikes RVM, Haxe, Rubinius, and Scala), and the SHIM profiler.

Dr. McKinley is an IEEE Fellow and ACM Fellow. Her research has garnered Test-of-Time awards (ASPLOS, OOPSLA (2), SIGMETRICS, ICS), best paper awards (Middlewear, ASPLOS), IEEE MICRO Top Picks awards (4), SIGPLAN Research Highlights, NVMW Memorable Paper, and CACM Research Highlights (2). Dr. McKinley was honored to testify to the House Science Committee (Feb. 14, 2013).  She has graduated 22 PhD students. She and her husband have three sons. She is passionate about improving research culture and widening participation from under represented groups.

Favorite quote: “I have missed more than 9000 shots in my career. I have lost almost 300 games. On 26 occasions I have been entrusted to take the game winning shot… and missed. And I have failed over and over and over again in my life. And that is why I succeed.” — Michael Jordan

Time: March 17th, 2020 (Tuesday), Noon-1pm (US Eastern)


Title: Demystifying Grad School (Video)

Time: March 19th, 2020 (Thursday), 11am-12:30pm (US Eastern)

Panelist: Anastasia Ailamaki

Affiliation: EPFL and RAW Labs SA

Interests: JIT analytical engines, scale-out HTAP, accelerator-level parallelism.

Bio: Anastasia Ailamaki is a Professor of Computer and Communication Sciences at EPFL and the CEO and co-founder of RAW Labs SA, a Swiss company that develops enables digital transformation for entreprises through real-time analysis of heterogeneous big data. Previously, she was on the faculty of the Computer Science Department at CMU, where she held the Finmeccanica endowed chair. She has received the 2019 ACM SIGMOD Edgar F. Codd Innovations Award, the 2019 EDBT Test of Time award, the 2018 Nemitsas Prize in Computer Science, an ERC Consolidator Award (2013), the European Young Investigator Award from the European Science Foundation (2007), an Alfred P. Sloan Research Fellowship (2005), and ten best-paper awards in database, storage, and computer architecture conferences. She is an ACM fellow, an IEEE fellow, and an elected member of the Swiss, the Belgian, and the Cypriot National Research Councils.

Panelist: Irina Calciu

Affiliation: VMware Research

Interests: Parallel and distributed systems and algorithms, rack-scale systems, multicore synchronization, concurrent data structures, hardware support for rack-scale systems

Bio: Irina Calciu is a senior researcher at VMware Research working on systems and algorithms for rack-scale computing. Irina has co-authored papers at top conferences, obtaining Best Paper awards at ASPLOS and TRANSACT, and was awarded a Kanellakis Fellowship in 2014. Irina completed her PhD at Brown University in 2015, working with Maurice Herlihy and Justin Gottschlich (Intel Labs) on algorithms for non-uniform memory access (NUMA) architectures and hybrid transactional memory.  Prior to VMware, she has been a visiting researcher at Intel Labs and a research intern at Microsoft Research.

Panelist: Boris Grot

Affiliation: Univ. of Edinburgh

Interests: Datacenters, memory systems, computer networks, microarchitecture, quality-of-service in big-data systems, ML for systems.

Bio: Boris Grot is an Associate Professor (called “Reader” in UK) in the School of Informatics at the University of Edinburgh. His research seeks to address efficiency bottlenecks and capability shortcomings of processing platforms for data-intensive applications. Boris is a member of the MICRO Hall of Fame and a recipient of multiple awards for his research, including the Best Paper Award at HPCA 2019. Prior to starting at Edinburgh, he did a post-doc at EPFL. Boris holds a PhD in Computer Science from The University of Texas at Austin, MSc from UCLA, and a Bachelor’s from Penn State University. Along the way, Boris interned at Microsoft Research, nVidia and Intel, and had a full-time stint as a hardware engineer in the telecom sector.

Panelist: Gabriel H. Loh

Affiliation: AMD Research

Interests: Computer architecture, processor microarchitecture, emerging technologies, 3D die stacking.

Bio: Gabriel H. Loh is a Senior Fellow in and the Chief Scientist for AMD Research, the research and advanced development lab for Advanced Micro Devices, Inc. Gabe received his Ph.D. and M.S. in computer science from Yale University in 2002 and 1999, respectively, and his B.Eng. in electrical engineering from the Cooper Union in 1998. Gabe was also a tenured associate professor in the College of Computing at the Georgia Institute of Technology, a visiting researcher at Microsoft Research, and a senior researcher at Intel Corporation. He is a Fellow of the ACM and IEEE, recipient of ACM SIGARCH’s Maurice Wilkes Award, Hall of Fame member for the MICRO, ISCA, and HPCA conferences, (co-)inventor on over one hundred US patent applications and eighty granted patents, and a recipient of the US National Science Foundation Young Faculty CAREER Award.

Panelist: Gilles Pokam

Affiliation: Intel

Interests: Computer architecture and its interactions with security, systems software and applications; performance analysis and simulation.

Bio: Gilles Pokam is a Principal Engineer at Intel Labs, where he currently leads research on developing novel microarchitecture mechanisms for next generation processor front-end and security. He has a broad interest in computer architecture related topics, in particular on their interactions with application software and systems.  Prior to joining Intel Labs, he was a researcher at IBM T.J. Watson Research Center in NY, and a postdoctoral researcher at University of California, San Diego. He received his PhD in Computer Engineering from INRIA, in France. He has published numerous papers in tier one computer architectures and systems software conferences, and holds 30+ patents. He is the recipient of the 2006 IEEE Top Picks Award.

Panel Moderator: Akshitha Sriraman

Affiliation: Univ. of Michigan

Interests: Computer architecture and systems software, focusing on designing efficient hyperscale web systems.

Bio: Akshitha’s research improves the performance, cost, and energy efficiency of hyperscale web services. Current web service systems introduce trade-offs between performance and numerous features essential for cost- and energy-efficient operation of data centers (e.g., high server utilization, continuous power management, and use of commodity hardware and software). Specifically, she has designed and implemented practical and scalable systems that improve service performance across the system stack, without sacrificing cost- and energy-efficiency in modern hyperscale web systems.

Akshitha is a UIUC Rising Stars in EECS Workshop participant and a recipient of the Rackham Graduate Fellowship. Her work has resulted in multiple research papers at top-tier computer architecture and systems venues like OSDI, ISCA, and ASPLOS.


The central theme of this workshop is to serve as a welcoming venue for junior graduate students to present their ongoing work and receive feedback from experts within the community. In addition, this workshop also aims to help early-stage graduate students in building connections both with their peers and established architects in the community. To this end, YArch will include:

Route to Top-tier: Each submitted work will receive two or more expert reviews. The aim of these reviews will be to give early guidance on important boxes to check for the submitted work to be a future successful top tier conference paper.

Meet an Architect: As part of the workshop, attendees will be paired with experts in their chosen research area to get feedback on their ongoing work and future research directions.

Becoming an Architect: The workshop will include keynote talks from academic and industry leaders specifically geared towards early stage graduate students.

Ask an Architect: The workshop will include a panel of established architects in industry and academia from whom students can seek career advice.


YArch strives to be an inclusive and diverse venue for Young Architects and below are some statistics to show how we performed along this dimension at YArch’19. Future versions for YArch will strive to improve in this regard.

– Five out of ten accepted student submissions were from female students.
– Of the two keynote speakers, one is from industry and one from academia, including one female speaker.
– Of the five panelists, three are from industry and two from academia, including two female panelists.
– Of the two workshop organizers,  one is from industry and one from academia, including one female organizer.
– Of the twenty nine PC members, nine are from industry and twenty from academia, including six female members.

Travel support

YArch is committed to providing significant travel support to students accepted at the workshop. We will strive to cover the full cost of attendance for workshop participants. A couple of other clarifications:

– Students accepted to YArch through our submission will be eligible for YArch travel grants and these travel grants will be processed after YArch acceptance notifications are sent out. These are separate from ASPLOS conference travel grants, however, students would receive at most one of the two kinds of travel grants.
– Given our current levels of sponsorship, we expect YArch travel grants to be over 1,000 USD. We are working to raise more sponsorships.
– While issuing YArch travel grants, students without prior first author ISCA/MICRO/ASPLOS/HPCA papers will be prioritized.


Eligibility: Applicants must be graduate students (Ph.D or Masters) in computer architecture and related fields who have completed less than 3 years of graduate school (Masters and/or PhD) at the time of the workshop. A note from the student’s research advisor attesting this is required as part of the submission.

Call for Submissions: Eligible students are invited to submit their early stage or on-going work to this workshop. Submitted work should not have been presented as part of a prior ACM/IEEE conference.

The workshop invites papers from all areas of computer architecture, broadly defined. Topics of interest include, but not limited to:
– Datacenter systems
– Hardware acceleration
– Memory hierarchy
– Virtualization
– Security
– Microarchitecture
– GPUs
– Parallel architectures
– Emerging technologies

Note: This workshop is not a venue for publication and there will be no formal proceedings.

Submission guidelines: The goal of this workshop is to help students think about a problem/idea in an holistic manner and communicate your ideas to the wider community, so that we can provide some valuable early-stage feedback. To this end, we encourage you to cover the following aspects in your submission:

Scope of problem/idea: Provide clear context for and scope of the problem(s) or idea(s) you intend to work on. This will likely form the basis of the introduction/background sections of your future work(s).

Solution: Provide an overview of the design and implementation aspects of your solution(s) to the problem(s) described above. Given this is on-going work, focus more on providing breadth than depth. For example, beside describing the design of your idea, enlist the various system aspects which your proposed solutions will affect (e.g. does your proposed solution affect coherence protocols?) and that if you plan to discuss these effects in your future submission(s).

Evaluation methodology: Discuss the evaluation methodology you plan to adopt to test the efficacy of your ideas. For example, the workloads that you plan to use, the tools you’ll employ (e.g., architectural simulator, real world experiments, FPGA prototypes), etc.

Related work: This can be the traditional related work section. Please specify if you plan to quantitatively compare against some prior work. 

Submission details
– Submissions must be PDF files, in 2-column, single-spaced, 10pt format.
– Submissions must be at most 2 pages long, not including references.
Submissions are double-blind. Please do not have any author identifying information in the paper submitted.
– Please have your research advisor send the workshop organizers an email with the following subject line “<Your name> meets YArch’20 eligibility requirements” to “yarch.asplos20@gmail.com”.
– Submission site: Link
– Submission deadline: January 24th 2020 (Friday), 11:59pm (Pacific)

Declaring conflicts: When registering a submission, all its co-authors must provide information about conflicts with the YArch ’20 program committee members. You are conflicted with a member if: (1) you are currently employed at the same institution, have been previously employed at the same institution within the past two years (2016 or later), or are going to begin employment at the same institution; (2) you have a past or present association as thesis advisor or advisee (no time limit); (3) you have collaborated on a project, publication, grant proposal, or editorship within the past two years (2016 or later); or (4) you have spouse or first-degree relative relations.

To be updated.



Shaizeen Aga, AMD Research

Aasheesh Kolli, Pennsylvania State University

Alexandros Daglis, Georgia Tech.


Mohammad Shahrad, Princeton University

Akshitha Sriraman, University of Michigan

Program Committee:

John Alsop, AMD Research
Arkaprava Basu, Indian Institute of Science, Bangalore
Rangeen Basu Roy Chowdhury, Intel
Jason Clemons, NVidia
Joseph Devietti, University of Pennsylvania
Christopher Fletcher, University of Illinois Urbana-Champaign
Shrikanth Ganapathy, AMD Research
Jayneel Gandhi, VMWare
Suagata Ghose, Carnegie Mellon University
Boris Grot, University of Edinburgh
Akanksha Jain, University of Texas at Austin
Nuwan Jayasena, AMD Research
Onur Kayiran, AMD Research
Samira Khan, University of Virginia
Vincent T. Lee, Facebook
Andrew Lukefahr, Indiana University
Divya Mahajan, Microsoft Research
Prashant Nair, University of British Columbia
Tony Nowatzki, UCLA
Gokul Subramanian Ravi,  University of Wisconsin-Madison
Brandon Reagen, NYU/Facebook
Adrian Sampson, Cornell
Joshua San Miguel, University of Wisconsin-Madison
Abhayendra Singh, Google LLC
Akshitha Sriraman, University of Michigan/ Facebook/ Harvard
Swamit Tannu, Georgia Institute of Technology
Ashish Venkat, University of Virginia
Radha Venkatagiri, University of Illinois Urbana-Champaign
Vivek V Menon, University of Southern California-Information Sciences Institute
Rujia Wang, Illinois Institute of Technology
Daniel Wong, University of California, Riverside
Mengjia Yan, MIT
Jishen Zhao, University of California, San Diego
Yuhao Zhu, University of Rochester