Class Detail: This class builds a foundation of digital VLSI. The course includes CMOS technology, logic gates, DC and transient response of an inverter, logical effort theory, interconnects, adder families, sequential circuits, delay/power analysis, multipliers, and DRAM/SRAM. This course is full of content and relatively complex.
Instructor: Swaroop Ghosh
In this class, I have learned comprehensive knowledge about digital VLSI. I also learned typical digital circuit design workflow using Cadence Virtuoso. The class involves two phases of the adder project. The first part is designing and analyzing an 8-bit ripple carry adder. I finished the schematic, layout, and extraction of the design. After the design is finished, I used the ADE L to analyze worst-case delay performance. Some featured screenshots for the one-bit component are:
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For the second project, I chose to do the Sklansky look-ahead adder structure. However, I was not able to finish the assembly of individual cells at the end. Instead, I finished each individual cell’s schematic, layout, and extraction. I do have the schematic of the final product. The whole project folder can be accessed here: Download Project Folder. Featured screenshot:
This class was difficult in both class content and project. But I do find fun during the project design because the process of digital circuit design feels like building a higher-end LEGO, with much more considerations in mind (although not involved in this class).