Publications

PATENTS

Xueqing Li, Sumitha George, John Sampson, Sumeet Gupta, Suman Datta, Vijaykrishnan Narayanan, Kaisheng Ma. Nonvolatile digital computing with ferroelectric FET. US Patent 10475514
Sumeet Kumar Gupta, Ahmedullah Aziz, Nikhil Shukla, Suman Datta, Xueqing Li, Vijaykrishnan Narayanan. Low power sense amplifier based on phase transition material. US Patent 10262714.
Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta, Moon Seok Kim, Xueqing Li, Alexandre Schmid, Mahsa Shoaran, Unsuk Heo. Low power nanoelectronics. US Patent 9800094
Huichu Liu, Ramesh Vaddi, Vijaykrishnan Narayanan, Suman Datta. Power rectifier using tunneling field effect transistor. US Patent 9391068
Vinay Saripalli, Dheeraj Mohata, Saurabh Mookherjea, Suman Datta, Vijaykrishnan Narayanan. TFET based 4T memory devices. US Patent 8638591
Jawar Singh, Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, Vijaykrishnan Narayanan. TFET based 6T SRAM cell. US Patent 8369134
M. Irick, Vijaykrishnan Narayanan, Hankyu Moon, Rajeev Sharma and Namsoon Jung. Apparatus and method for hardware implementation of object recognition from an image stream using artificial neural network, US Patent 8081816
M. Irick, Vijaykrishnan Narayanan, Hankyu Moon, Rajeev Sharma and Namsoon Jung. Apparatus and method for measuring audience data from image stream using dynamically-configurable hardware architecture. US Patent 8165386.

JOURNALS

Z Shen, S Srinivasa, A Aziz, S Datta, V Narayanan, SK Gupta. SRAMs and DRAMs With Separate Read–Write Ports Augmented by Phase Transition Materials. IEEE Transactions on Electron Devices 66 (2), 929-937 (2019)
Xueqing Li, Juejian Wu, Kai Ni, Sumitha George, Kaisheng Ma, John Sampson, Sumeet Kumar Gupta, Yongpan Liu, Huazhong Yang, Suman Datta, Vijaykrishnan Narayanan. Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs. IEEE Design & Test 36(3): 39-45 (2019)
Arijit Raychowdhury, Abhinav Parihar, Gus Henry Smith, Vijaykrishnan Narayanan, György Csaba, Matthew Jerry, Wolfgang Porod, Suman Datta. Computing With Networks of Oscillatory Dynamical Systems. Proceedings of the IEEE 107(1): 73-89 (2019)
Srivatsa Rangachar Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei-Hao Chen, Sumeet Kumar Gupta, Meng-Fan Chang, Swaroop Ghosh, Jack Sampson, Vijaykrishnan Narayanan. ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support. IEEE Trans. on Circuits and Systems 66-I(7): 2533-2545 (2019)
Kaisheng Ma, Jinyang Li, Xueqing Li, Yongpan Liu, Yuan Xie, Mahmut T. Kandemir, Jack Sampson, Vijaykrishnan Narayanan. IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors. IEEE Micro 38(4): 11-19 (2018)
Xueqing Li, Sumitha George, Kaisheng Ma, Kai Ni, Ahmedullah Aziz, Sumeet Gupta, John Sampson, Meng-Fan Chang, Yongpan Liu, Huazhong Yang, Suman Datta, and Vijaykrishnan Narayanan. Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops. IEEE Transactions on Electron Devices, accepted.
Sumitha George, Xueqing Li, Minli Julie Liao, Kaisheng Ma, Srivatsa Srinivasa, Karthik Mohan, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, and Vijaykrishnan Narayanan. Symmetric 2-D-Memory Access to Multidimensional Data. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, doi: 10.1109/TVLSI.2018.2801302.
Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, Kamakoti: An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators. JETC 14(1): 1:1-1:28 (2018)
Srivatsa Rangachar Srinivasa, Xueqing Li, Meng-Fan Chang, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan: Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration. IEEE Trans. VLSI Syst. 26(4): 671-683 (2018)
Xueqing Li; John Sampson; Asif Khan; Kaisheng Ma; Sumitha George; Ahmedullah Aziz; Sumeet Kumar Gupta; Sayeef Salahuddin; Meng-Fan Chang; Suman Datta; Vijaykrishnan Narayanan. Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET. IEEE Transactions on Electron Devices 2017, 64(8): 3452 – 3458
Shreya Gupta; Mark Steiner; Ahmedullah Aziz; Vijaykrishnan Narayanan; Suman Datta; Sumeet Kumar Gupta. Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic. IEEE Transactions on Electron Devices. 2017, 64(8): 3092 – 3100
Xueqing Li; Kaisheng Ma; Sumitha George; Win-San Khwa; John Sampson; Sumeet Gupta; Yongpan Liu; Meng-Fan Chang; Suman Datta; Vijaykrishnan Narayanan. Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore. IEEE Transactions on Electron Devices. 2017. 64(7): 3037 – 3040
Xueqing Li; Sumitha George; Kaisheng Ma; Wei-Yu Tsai; Ahmedullah Aziz; John Sampson; Sumeet Kumar Gupta; Meng-Fan Chang; Yongpan Liu; Suman Datta; Vijaykrishnan Narayanan. Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops. IEEE Transactions on Circuits and Systems I: Regular Papers. 2017, 13 pages.
Peter A. Zientara, Sooyeon Lee, Gus H. Smith, Rorry Brenner, Laurent Itti, Mary Beth Rosson, John M. Carroll, Kevin M. Irick, Vijaykrishnan Narayanan. Third Eye: A Shopping Assistant for the Visually Impaired. IEEE Computer 50(2): 16-24 (2017)
Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan. Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. VLSI Syst. 25(4): 1477-1489 (2017)
Xiao, Y., Advani, S., Shin, D., Chang, N., Sampson, J., & Narayanan, V. (Author) (2016). A Saliency-Driven LCD Power Management System. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(8), 2689–2702. (First and second author supervised)
Tsai, W.-Y., Barch, D., Cassidy, A., Debole, M., Andreopoulos, A., Jackson, B., Flickner, M., Arthur, J., Modha, D., Sampson, J., & Narayanan, V. (Author) (2016). Always-on Speech Recognition using TrueNorth, a Reconfigurable, Neurosynaptic Processor. IEEE Transactions on Computers(99). (First Author co-supervised)
Ho, C.-H., Chen, Y.-C., Wang, C.-Y., Huang, C.-Y., Datta, S., & Narayanan, V. (Author) (2016). Area-Aware Decomposition for Single-Electron Transistor Arrays. ACM Transactions on Design Automation of Electronic Systems (TODAES), 21(4), 70.
Kim, M. S., Cane-Wissing, W., Li, X., Sampson, J., Datta, S., Gupta, S., & Narayanan, V. (Author) (2016). Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells. ACM Journal on Emerging Technologies in Computing Systems (JETC), 12(4), 38. (First Author supervised)
Srinivasa, S., Aziz, A., Shukla, N., Li, X., Sampson, J., Datta, S., Kulkarni, J. P., Narayanan, V. (Author), & Gupta, S. (2016). Correlated Material Enhanced SRAMs With Robust Low Power Operation. IEEE Transactions on Electron Devices, 63(12), 4744–4752. (First Author co-supervised)
Huang, C.-Y., Li, Y.-J., Liu, C.-W., Wang, C.-Y., Chen, Y.-C., Datta, S., & Narayanan, V. (Author) (2016). Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(6), 2321–2334.
Tsai, W.-Y., Li, X., Jerry, M., Xie, B., Shukla, N., Liu, H., Chandramoorthy, N., Cotter, M., Raychowdhury, A., Chiarulli, D. M., Levitan, S. P., Datta, S., Sampson, J., Ranganathan, N., & Narayanan, V. (2016). Enabling new computation paradigms with hyperFET-an emerging device. IEEE Transactions on Multi-Scale Computing Systems, 2(1), 30–48. (First author supervised)
Kim, M. S., Li, X., Liu, H., Sampson, J., Datta, S., & Narayanan, V. (Author) (2016). Exploration of low-power high-SFDR current-steering D/A converter design using steep-slope heterojunction Tunnel FETs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(6), 2299–2309. (First author supervised)
Sun, Y., Yuan, Z., Liu, Y., Li, X., Wang, Y., Wei, Q., Wang, Y., Narayanan, V. (Author), & Yang, H. (2016). Maximum Energy Efficiency Tracking Circuits for Converter-less Energy Harvesting Sensor Nodes. IEEE Transactions on Circuits and Systems II: Express Briefs. (Fourth author supervised)
Ma, K., Li, X., Swaminathan, K., Zheng, Y., Li, S., Liu, Y., Xie, Y., Sampson, J., & Narayanan, V. (Author) (2016). Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power. IEEE Micro, 36(3), 72–83. (First Author co-supervised, second author supervised)
Sustersic, J., Wyble, B., Advani, S., & Narayanan, V. (Author) (2016). Towards a unified multiresolution vision model for autonomous ground robots. Robotics and Autonomous Systems, 75, 221–232. http://dx.doi.org/10.1016/j.robot.2015.09.031. (Third author supervised)
Kaisheng Ma, Xueqing Li, Shuangchen Li, Yongpan Liu, John (Jack) Morgan Sampson, Yuan Xie, Vijaykrishnan Narayanan:Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications. IEEE Micro 35(5): 32-40 (2015) (First Author co-supervised, second author supervised)
Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan: Synthesis for Width Minimization in the Single-Electron Transistor Array. IEEE Trans. VLSI Syst. 23(12): 2862-2875 (2015)
Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, and Yuan Xie, “Optimizing the NoC Slack through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cho, N. Chandramoorthy, K.M. Irick, V. Narayanan, “Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications”, in Journal of Signal Processing Systems Volume 76, Issue 2, Aug. 2014 (First three authors supervised)
Moon Seok Kim, Huichu Liu, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan, “A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter,” IEEE Transactions on Electron and Devices, 6 pages. (First author supervised and second author co-supervised)
Shukla, A. Parihar, E. Freeman, H. Paik, G. Stone, V. Narayanan, H. Wen, Z. Cai, V. Gopalan, R. Engel-Herbert, D. G. Schlom, A. Raychowdhury, and S. Datta “Synchronized charge oscillations in correlated electron systems”, Scientific Reports 4:4964, May 14, 2014.
Pandey, V. Saripalli, J. Kulkarni, S. Datta, V. Narayanan, “Impact of single trap random telegraph noise on heterojunction TFET SRAM stability” in IEEE Electron Device Letters, vol. 35, no. 3, pp. 393–395, Mar. 2014. (Second author co-supervised)
Huichu Liu, Xueqing Li, Ramesh Vaddi, Kaisheng Ma, Suman Datta and Vijaykrishnan Narayanan, “Tunnel FET RF Rectifier Design for Energy Harvesting Application”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2014, (First author co-supervised and next three authors supervised).
Huichu Liu, M. Cotter, S. Datta and V. Narayanan, “Soft Error Performance Evaluation on Emerging Low Power Devices”, IEEE Transactions on Device and Materials Reliability (TDMR), vol.14, no.2, pp.732,741, June 2014. (first author co-supervised, second author supervised)
Suman Datta, Huichu Liu, V. Narayanan, “Tunnel FET Technology: A Reliability Perspective”, Microelectronics Reliability (MR), Vol. 54, Iss. 5, Pages 861–874, May 2014.
Pandey, R. Bijesh, Huichu Liu, V. Narayanan, S. Datta, “Electrical Noise in Heterojunction Interband Tunnel FETs”, IEEE Transactions on Electronic Devices (TED), vol.61, no.2, pp.552,560, Feb. 2014. (Third author co-supervised)
Yung-Chih Chen, Soumya Eachempati, Chun-Yao Wang, Suman Datta, Yuan Xie, Vijaykrishnan Narayanan: A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays. JETC 9(1): 5 (2013) (Second author supervised)
Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta: Steep-Slope Devices: From Dark to Dim Silicon. IEEE Micro 33(5): 5059 (2013) (First author supervised)
Ahmed Al-Maashri, Matthew Cotter, Nandhini Chandramoorthy, Michael DeBole, Chi-Li Yu, Vijaykrishnan Narayanan, Chaitali Chakrabarti: Hardware Acceleration for Neuromorphic Vision Algorithms. Signal Processing Systems 70(2): 163-175 (2013) (First four authors supervised)
Liu, L., N. Vijaykrishnan, S. Datta. February 2013. A Programmable Ferroelectric Single Electron Transisistor. Applied Physics Letters. Volume 102, Issue 5, 4 pages.
Yang, S., P. Gupta, M. Wolf, D. Serpanos, Y. Xie, N. Vijaykrishnan. September 2012. Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. ACM Transactions on Embedded Computing Systems (TECS). Volume 11, Issue 3, Article 62.
Singh, P. N. Vijaykrishnan, D. Landis. June 2012. Targeted Random Test Generation for Power-aware Multicore Designs. ACM Transactions on Design Automation of Electronic Systems. Volume 17, Number 3, 25 pages.
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. October 2011. Soft Error Modeling and Analysis of the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Phsyics Research A 652(1):370-373.
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. October 2011. Cosmic Ray Background Effects on the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Phsyics Research A 652(1):338-341.
Yu, C.-L., J. S. Kim, L. Deng, S. Kestur*, N. Vijaykrishnan, C. Chakrabarti. July 2011. FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data. Journal of Signal Processing Systems 64(1):109-122. (Fourth author co-supervised by candidate)
Saripalli, V., G. Sun, A. Mishra, Y. Xie, S. Datta and N. Vijaykrishnan. June 2011. Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors. IEEE Journal on Emerging and Selected Topics in Circuits and Systems 1(2). (INVITED)
Wang, F. Chen, C. Nicopoulos, X. Wu, Y. Xie, N. Vijaykrishnan. 2011. Variation-Aware Task and Communication Mapping for MPSoC Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 295-307.
Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. Narayanan, A. Liu and S. Datta. Feb 2011. Experimental Staggered-Source and N+ Pocket-Doped Channel III-V Tunnel Field-Effect Transistors and Their Scalabilities. Applied Physics Express, Vol. 4, pp. 024105, February 2011
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. 2010. Soft Error Modeling and Analysis of the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Physics Research A. Volume 652(1) p. 370-373
Celik, C., K. Unlu, N. Vijaykrishnan, M. J. Irwin. 2010. Cosmic Ray Background Effects on the Neutron Intercepting Silicon Chip (NISC). Nuclear Instruments and Methods in Phsyics Research A. 652(1), p. 338-341
Yu, C-L, K. Irick*, C. Chakrabarti, V. Narayanan. December 2010. Multidimensional DFT IP Generator for FPGA Platforms. IEEE Transactions on Circuits and Systems. Online at IEEE Explore – Digital Object Identifier 10.1109/TCSI.2010.2078750. (Second author supervised by candidate)
Mishra A.K, A. Yanamandra*, R. Das, S. Eachempati, R. Iyer, N. Vijaykrishnan and C. Das. December 2010. RAFT: A Router Architecture with Frequency Tuning for On-chip Networks. Journal of Parallel and Distributed Computing. Online at Elsevier Science – Digital Object Identifier:10.1016/j.jpdc.2010.09.005. (Second author co-supervised by candidate)
Saripalli*, V, L. Liu, S. Datta, and V. Narayanan. October 2010. Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits. Journal of Low Power Electronics 6:415-428. (First author co-supervised by candidate)
Nicopoulos*, C. A., S. Srinivasan*, A. Yanamandra*, D. Park, N. Vijaykrishnan, C. R. Das, M. J. Irwin. July-September 2010. On the Effects of Process Variation in Network-on-Chip Architectures. IEEE Transactions on Dependable and Secure Computing (TDSC) 7(3):240-254. (First two authors supervised and third author co-supervised by candidate)
Mookerjea, S., D. Mohata, T. Mayer, N. Vijaykrishnan, S. Datta. June 2010. Temperature-Dependent I-V Characteristics of a Vertical In0.53Ga0.47AS Tunnel FET. IEEE Electron Device Letters 31(6):564-566.
Hung, W-L., Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2010. Total Power Optimization for Combinational Logic Using Genetic Algorithms. Journal of VLSI Signal Processing Systems 58(2):145-160.
Kim*, J. S., P. Mangalagiri*, K. Irick*, M. Kandemir, N. Vijaykrishnan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun. December 2009. An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. IEEE Transactions on Computers 58(12):1654-1667. (First and third authors supervised and second author co-supervised by candidate)
Mookerjea, S., R. Krishnan*, S, Datta, N. Vijaykrishnan. October 2009. On Enhanced Miller Capacitance Effect in Inter-Band Tunnel Transistors. IEEE Electron Device Letters 30(10):1102-1104. (Second author co-supervised by candidate)
Mookerjea, S., R. Krishnan*, S. Datta, N. Vijaykrishnan. September 2009. Effective Output Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation. IEEE Transactions on Electron Devices 56(9):2092-2098. (Second author co-supervised by candidate)
DeBole*, M., R. Krishnan*, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao, N. Vijaykrishnan. August 2009. New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. International Journal of Parallel Programming 37(4):417-431. (First two authors co-supervised by candidate)
Ramanarayanan*, R., V. Degalahal*, R. Krishnan*, J. Kim*, N. Vijaykrishnan, Y. Xie, M. Irwin, K. Unlu. July-September 2009. Modeling Soft Errors at Device and Logic Level for Combinational Circuits. IEEE Transactions on Dependable and Secure Computing (TDSC) 6(3):202-216. (First and third authors co-supervised, second and fourth authors supervised by candidate)
Hu*, J., F. Li, V. Degalahal*, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. July 2009. Compiler-assisted Soft Error Detection under Performance and Energy Constraints in Embedded Systems. ACM Transactions on Embedded Computing Systems 8(4):27.1-27.29. (First and third authors supervised by candidate)
Mutyam*, M., F. Wang, R. Krishnan*, N. Vijaykrishnan, M. Kandemir, Y. Xie, M. J. Irwin. July 2009. Process Variation Aware Adaptive Cache Architecture and Management. IEEE Transactions on Computers 58(7):865-877. (First author supervised and third author co-supervised by candidate)
Eachempati*, S., N. Vijaykrishnan, A. Nieuwoudt, Y. Massoud. April 2009. Predicting the Performance and Reliability of Future Field Programmable Gate Arrays Routing Architectures with Carbon Nanotube Bundle Interconnect. IET Circuits, Devices, & Systems 3(2):64-75. (First author co-supervised by candidate)
Ragheb, T., A. Ricketts*, M. Modal, S. Kirolos, G. Link*, N. Vijaykrishnan, Y. Massoud. February 2009. Design of Thermally Robust Clock Trees using Dynamically Adaptive Clock Buffers. IEEE Transactions on Circuits and Systems (TCAS) 56(2):374-383. (Second and fifth authors supervised by candidate)
Srinivasan*, S., F. Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini. September 2008. Exploring Architectural Solutions for Energy Optimizations in Bus Based SoC. IET Computers & Digital Techniques 2(5):347-354.
Celik, C., K. Unlu, K. Ramakrishnan*, R. Rajaraman*, N. Vijaykrishnan, M. J. Irwin, Y. Xie. August 2008. Thermal Neutron Induced Soft Error Rate Measurement in Semiconductor Memories and Circuits. Journal of Radioanalytical and Nuclear Chemistry 278(2):509-512. (Third author supervised and fourth author co-supervised by candidate)
Gayasen*, A., N. Vijaykrishnan, M. Kandemir, A. Rahman. July 2008. Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. IEEE Transactions on VLSI 16(7):882-893. (First author co-supervised by candidate)
Yang, S., W. Wang, T. Lu, W. Wolf, N. Vijaykrishnan, Y. Xie. July 2008. Case Study of Reliability-Aware and Low-Power Design. IEEE Transactions on Very Large Scale Integration (VLSI) 16(7):861-873.
Srinivasan*, S., R. Krishnan*, P. Mangalagiri*, Y. Xie, N. Vijaykrishnan, M. J. Irwin, K. Sarpatwari. April-June 2008. Toward Increasing FPGA Lifetime. IEEE Transactions on Dependable and Secure Computing 5(2):115-127. (Third and third authors supervised and second author co-supervised by candidate)
Tsai*, Y., F. Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin. April 2008. Design Space Exploration for Three-Dimensional Cache. IEEE Transactions on VLSI 16(4):444-455. (First author supervised by candidate)
Brooks, R., P. Govindaraju, M. Pirretti*, N. Vijaykrishnan, M. Kandemir. November 2007. On the Detection of Clones in Sensor Networks Using Random Key Predistribution. IEEE Transactions on Systems, Man, and Cybernetics 37(6):1246-1258. (Third author supervised by candidate)
Xie, Y., L. Li*, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. October 2007. Reliability-Aware Co-synthesis for Embedded Systems. Journal of VLSI Signal Processing 49(1):87-99. (Second author supervised by candidate)
Wang, F., M. Debole*, X. Wu, Y. Xie, N. Vijaykrishnan, M. J. Irwin. September 2007. On-chip Bus Thermal Analysis and Optimization. IET Computer & Digital Techniques 1(5):590-599. (Second author co-supervised by candidate)
Kim*, S., N. Vijaykrishnan, M. J. Irwin. August 2007. Reducing Non-Deterministic Loads in Low-Power Caches via Early Cache Set Resolution. Microprocessors and Microsystems 31(5):293-301. (First author supervised by candidate)
Hu*, J., N. Vijaykrishnan, M. J. Irwin, M. Kandemir. July 2007. Optimizing Power Efficiency in Trace Cache Fetch Unit. IET Computers and Digital Techniques 1(4):334-348. (First author supervised by candidate)
Gayasen*, S. Srinivasan*, N. Vijaykrishnan, M. Kandemir. 2007. Design of Power-Aware FPGA Fabrics. International Journal of Embedded Systems 3(1/2):52-64. (First author co-supervised and second author supervised by candidate)
Pirretti*, M., S. Zhu, N. Vijaykrishnan, P. McDaniel, M. Kandemir, R. Brooks. September 2006. The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense. International Journal of Distributed Sensor Networks 2(3):267-287. (First author supervised by candidate)
T., J. Rubio, L. K. John, A. Sivasubramaniam, N. Vijaykrishnan. January 2007. OS-aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems. IEEE Transactions on Computers 56(1):2-17.
Lee*, J., N. Vijaykrishnan, M. J. Irwin. July 2006. Block-Based Frequency Scalable Technique for Efficient Hierarchical Coding. IEEE Transactions on Signal Processing 54(7):2559-2566. (First author co-supervised by candidate)
Lee*, J., N. Vijaykrishnan, M. J. Irwin. May 2006. Efficient VLSI Implementation of Inverse Discrete Cosine Transform. IEEE Transactions on Circuits and Systems for Video Technology 16(5):655-662. (First author co-supervised by candidate)
Lee*, J., N. Vijaykrishnan, M. J. Irwin, W. Wolf. February 2006. An Efficient Architecture for Motion Estimation and Compensation in the Transform Domain. IEEE Transactions on Circuits and Systems for Video Technology 16(2):191-201. (First author co-supervised by candidate)
Zhang, W., Y-F Tsai*, D. Duarte, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2006 Reducing Dynamic and Leakage energy in VLIW Architectures. ACM Transactions on Embedded Computing Systems 5(1):1-28. (Second author supervised by candidate)
Vijaykrishnan, N., Xie, Y. January 2006. Reliability concerns in embedded system designs. IEEE Computer. 39(1):118-120. (Invited) (Principal author)
Swankowski, E., N. Vijaykrishnan, R. Brooks, M. Kandemir, M. J. Irwin. Symmetric Encryption in Reconfigurable and Custom Hardware. International Journal of Embedded Systems 1(3/4):205-217. (First author supervised by candidate)
Lattanzi, E, A. Gayasen, M. Kandemir, N. Vijaykrishnan, L. Benini, A. Bogliolo. 2005 Improving Java performance using dynamic method migration on FPGAs. International Journal of Embedded Systems 1(3/4):228-236. (First author supervised and second author co-supervised by candidate)
Hu, J. S., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. November 2005. Analyzing Data Reuse for Cache Reconfiguration. ACM Transactions on Embedded Computing Systems 4(4):851-876. (First author supervised by candidate)
Kadayif, I., M. Kandemir, G. Chen, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam. November 2005. Compiler-directed High-level Energy Estimation and Optimization. ACM Transactions on Embedded Computing Systems (TECS) 4(4):819-850.
Degalahal, V., L. Li, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. October 2005. Soft Error Issues in Low Power Caches. IEEE Transactions on VLSI 13(10):1157-1166. (First author supervised and second author co-supervised by candidate)
Murali, S., T. Theocharides, N. Vijaykrishnan, M. J. Irwin, L. Benini, G. DeMicheli. September-October 2005. Analysis of Error Recovery Schemes for Networks-On-Chips. IEEE Design and Test of Computers, Special Issue on Networks on Chips 22(5):434-442. (Second author co-supervised by candidate)
Kim, S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. July 2005. Exploiting Temporal Loads for Low Latency and High Bandwidth Memory. IEE Proceeding: Computers and Digital Techniques 152(4):457-455. (First author supervised by candidate)
Kim, E-J. G. Link, K. H. Yum, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, C. R. Das. June 2005. A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. IEEE Transactions on Computers 54(6):660-671. (Second author supervised by candidate)
Yang, S., W. Wolf, N. Vijaykrishnan. June 2005. Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. IEEE Transactions on Computers 54(6):714-726. (25% contribution)
Zhang, W., Y-F. Tsai, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, V. De. March 2005. Leakage-Aware Compilation for VLIW Architectures. IEE Proceedings: Computers and Digital Techniques 152(2):251-260. (Second author co-supervised by candidate) (Invited) (Equal contributions)
Kadayif, I., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. March 2005. An Integar Linear Programming Based Tool for Wireless Sensor Networks. Journal of Parallel and Distributed Computing (JPDC) 65(3):247-260. (20% contribution)
Kim, S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. March 2005. Optimizing Leakage Energy Consumption in Cache Bitlines. Journal of Design Automation for Embedded Systems (DAEM) 9(1):5-18. (First author supervised by candidate)
Tsai, Y-F., D. Duarte, N. Vijaykrishnan, M. J. Irwin. November 2004. Characterization and Modeling of Run-Time Techniques for Leakage Power Reduction. IEEE Transactions on Very Large Scale Integration Systems 12(11):1221-1233. (First author co-supervised by candidate)
Chen, G., B. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, R. Chandramouli. September 2004. Studying Energy Tradeoffs in Off-loading Computation/Compilation in Java-enabled Mobile Devices. IEEE Transactions on Parallel and Distributed Systems (TPDS) 15(9):795-809. (Second author co-supervised by candidate)
Parikh, A., S. Kim, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. May 2004. Instruction Scheduling for Low Power. Journal of VLSI Signal Processing Systems 37(1):129-149. (Second author supervised by candidate) (Equal contributions by authors)
Zhang, W., J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. March 2004. Reducing Instruction Cache Energy Consumption Using a Compiler-based Strategy. ACM Transactions on Architecture Code Optimization (TACO) 1(1):3-33. (Second and third authors supervised by candidate)
Juran, J., A. R. Hurson, N. Vijaykrishnan, S. Kim. March 2004. Data Organization and Retrieval on Parallel Air Channels. ACM/Kluwer Wireless Networks (WINET) Journal 10(2):183-195. (Contributing author)
Kandemir, M., J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, A. Parikh. February 2004. A Compiler Based Approach for Dynamically Managing Scratch-pad Memories in Embedded Systems. IEEE Transactions on Computer Aided Design 23(2):243-260. (Contributing author)
Kim, S., S. Tomar, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. January 2004. Energy-Efficient Java Execution Using Local Memory and Object Co-location. IEE Proceedings: Computers and Digital Techniques 151(1):33-42. (First two authors supervised by candidate)
Kim, N., T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. S. Hu, M. J. Irwin, M. Kandemir, N. Vijaykrishnan. December 2003. Leakage Current: Moore’s Law Meets Static Power. IEEE Computer, Special Issue on Power- and Temperature-Aware Computing 36(12):68-75. (Equal contributions by authors) (Sixth author supervised by candidate)
Saputra, H., N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, W. Zhang. September 2003. Masking the Energy Behavior of Encryption Algorithms. IEE Proceedings: Computers and Digital Techniques 150(5):274-284. (First author co-supervised by candidate – 30% contribution) (Invited among best papers at DATE 2003).
Kim, S., N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin. May 2003. Partitioned Instruction Cache Architecture for Energy Efficiency. ACM Transactions on Embedded Computing Systems: Special Issue on Compilers, Architecture, and Synthesis for Embedded Systems 2(2):163-185. (First author supervised by candidate) (Selected among best papers from CASES 2001)
Li, L, I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, A. Sivasubramaniam. February 2003. Managing Leakage Energy in Cache Hierarchies. Journal of Instruction-level Parallelism, Volume 5. (First and third authors co-supervised by candidate) (Invited among best papers presented at PACT 2002)
Vijaykrishnan, N., M. Kandemir, M. J. Irwin, H. Kim, W. Ye. January 2003. Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. IEEE Transactions on Computers 52(1):59-76. (Equal contributions by authors) (Fourth author supervised by candidate)
Duarte, D., N. Vijaykrishnan, M. J. Irwin. December 2002. A Clock Power Model to Evaluate Impact of Architectural and Technology Optimizations. IEEE Transactions on VLSI 10(6):844-855. (30% contribution) (IEEE CAS Transactions on VLSI Best Paper Award)
An, N., S. Gurumurthi, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. December 2002. Energy-Performance Trade-Offs for Spatial Access Methods on Memory-Resident Data. International Journal on Very Large Databases 11(3):179-197. (Contributing author) (Invited among best papers presented at VLDB; 5 out of the 59 papers presented at VLDB were selected)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin and M. Wolczko. November 2002. Tuning Garbage Collection for Reducing Memory System Energy in an Embedded Java Environment. ACM Transactions on Embedded Computer Systems 1(1):27-55. (Equal contributions by authors)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin and W. Wolf. October 2002. Using Memory Compression for Energy Reduction in an Embedded Java System. Journal of Circuits, Systems and Computers 11(5):537-556. (Equal contributions by authors)
Kandemir, M., N. Vijaykrishnan, M. J. Irwin, W. Ye. December 2001. Influence of Compiler Optimizations on System Power. IEEE Transactions on VLSI Systems 9(6):801-804. (Equal contributions by authors)
De La Luz, V., M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin. November 2001. Hardware and Software Techniques for Controlling DRAM Power Modes. IEEE Transactions on Computers, Special Issue on Advances in High Performance Memory Systems 50(11):1154-1173. (Equal contributions by authors)
Radhakrishnan, R., N. Vijaykrishnan, L. K. John, A. Sivasubramaniam, J. Rubio, J. Sabarinathan. February 2001. Java Runtime Systems: Characterization and Architectural Implications. IEEE Transactions on Computers. 50(2):131-146. (40% contribution)
Esakkimuthu, G., H. S. Kim, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. February 2001. Investigating Memory System Energy Behavior Using Software and Hardware Optimizations. Special Issue in Low Power System Design of VLSI DESIGN. 12(2):151-165. (First/second author supervised by candidate)
Bishop, B., V. Lyuboslavsky, N. Vijaykrishnan, M. J. Irwin. February 2001. Design Considerations for Databus Charge Recovery. IEEE Transactions on Very Large Scale Integration Systems 9(1):104-106.(Second author supervised).
Vijaykrishnan, N., N. Ranganathan. November 2000. Supporting Object Accesses in a Java Processor. Proceedings of IEE – Computers and Digital Techniques Journal 147(6):435-443. (Principal author)
Chandramouli, R., N. Vijaykrishnan, N. Ranganathan. December 1998. Sequential Tests for Integrated Circuit Failure Analysis. IEEE Transactions on Reliability 47(4):463-471. (Equal contributions by authors)
Ranganathan, N., N. Vijaykrishnan, N. Bhavanishankar. August 1998. A Linear Array Processor with Dynamic frequency Clocking for Image Processing Applications. IEEE Transactions on Circuits and Systems for Video Technology. 8(4):435-445. (50% contribution)

CONFERENCES

Nicholas Jao, Srivatsa Srivinasa, Akshay Krishna Ramanathan, Minhwan Kim, John Sampson and Vijaykrishnan Narayanan. Technology-Assisted Computing-In-Memory Design for Matrix Multiplication Workloads. 15^th IEEE/ACM International Symposium on Nanoscale Architectures. 2019.
Sandeep Krishna Thirumala, Arnab Raha, Vijaykrishnan Narayanan, Vijay Raghunathan and Sumeet Gupta. Non-volatile Logic and Memory based on Reconfigurable Ferroelectric Transistors. 15th IEEE/ACM International Symposium on Nanoscale Architectures. 2019.
Srinivasa, Y.-N. Tu, X. Si, C.-X. Xue, C.-Y. Lee, F.-K. Hsueh, C.-H. Shen, J.-M. Shieh, W.-K. Yeh, A. K. Ramanathan, M.-S. Ho, J. Sampson, M.-F. Chang and V. Narayanan. .Monolithic 3D+-IC Based Reconfigurable Compute-in-Memory SRAM Macro, IEEE 2019 Symposia on VLSI Technology and Circuits
Cadareanu, N. Reddy, C. G. Almudever, A. Khanna, A. Raychowdhury, S. Datta, K. Bertels, V. Narayanan, M. Di Ventra, P.-E. Gaillardon. Rebooting Our Computing Models. Design Automation in Europe, 2019.
Jinhang Choi, Zeinab Hakimi, Philip W. Shin, Jack Sampson, Vijaykrishnan Narayanan. Context-Aware Convolutional Neural Network over Distributed System in Collaborative Computing. DAC 2019: 211:1-211:6
Nicholas Jao, Akshay Krishna Ramanathan, Abhronil Sengupta, John Sampson, Vijaykrishnan Narayanan. Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations. ISCAS 2019: 1-5
Srivatsa Rangachar Srinivasa, Wei-Hao Chen, Yung-Ning Tu, Meng-Fan Chang, Jack Sampson, Vijaykrishnan Narayanan. Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs. ISCAS 2019: 1-5
Shubham Rai, Srivatsa Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar. Emerging reconfigurable nanotechnologies: can they support future electronics? ICCAD 2018: 13
Sumitha George, Minli Julie Liao, Huaipan Jiang, Jagadish B. Kotra, Mahmut T. Kandemir, Jack Sampson, Vijaykrishnan Narayanan. MDACache: Caching for Multi-Dimensional-Access Memories. MICRO 2018: 841-854
Jake Eden, Thomas Kawchak, Vijaykrishnan Narayanan. Indoor Navigation using Text Extraction. SiPS 2018: 112-117
Nicholas Jao, Akshay Krishna Ramanathan, Srivatsa Rangachar Srinivasa, Sumitha George, John Sampson, Vijaykrishnan Narayanan. Harnessing Emerging Technology for Compute-in-Memory Support. ISVLSI 2018: 447-452
Jinhang Choi, Kevin M. Irick, Justin Hardin, Weichao Qiu, Alan L. Yuille, Jack Sampson, Vijaykrishnan Narayanan. Stochastic Functional Verification of DNN Design through Progressive Virtual Dataset Generation. ISCAS 2018: 1-5
Sandeep Krishna Thirumala, Arnab Raha, Hrishikesh Jayakumar, Kaisheng Ma, Narayanan Vijaykrishnan, Vijay Raghunathan, Sumeet Kumar Gupta. Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems. ISLPED 2018: 31:1-31:6
Srivatsa Rangachar Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei-Hao Chen, Fu-Kuo Hsueh, Chih-Chao Yang, Chang-Hong Shen, Jia-Min Shieh, Sumeet Kumar Gupta, Meng-Fan Marvin Chang, Swaroop Ghosh, Jack Sampson, Vijaykrishnan Narayanan. A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support. ISLPED 2018: 34:1-34:6
Jinhang Choi, Srivatsa Rangachar Srinivasa, Yasuki Tanabe, Jack Sampson, Vijaykrishnan Narayanan. A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs. ISVLSI 2018: 22-27
Kaisheng Ma, Xueqing Li, Mahmut Taylan Kandemir, Jack Sampson, Vijaykrishnan Narayanan, Jinyang Li, Tongda Wu, Zhibo Wang, Yongpan Liu, Yuan Xie:
NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing. ASPLOS 2018: 782-796
Peter A. Zientara, Jinhang Choi, Jack Sampson, Vijaykrishnan Narayanan:
Drones as collaborative sensors for image recognition. ICCE 2018: 1-4
Wei-Yu Tsai; Jinhang Choi; Tulika Parija; Priyanka Gomatam; Chita Das; John Sampson; Vijaykrishnan Narayanan. Co-training of feature extraction and classification using partitioned convolutional neural networks. 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).
Ahmedullah Aziz; Xueqing Li; Nikhil Shukla; Suman Datta; Meng-Fan Chang; Vijaykrishnan Narayanan; Sumeet Kumar Gupta. Low power current sense amplifier based on phase transition material. 2017 75th Annual Device Research Conference (DRC) 1 – 2
Srivatsa Rangachar Srinivasa; Karthik Mohan; Wei-Hao Chen; Kuo-Hsinag Hsu; Xueqing Li; Meng-Fan Chang; Sumeet Kumar Gupta; John Sampson; Vijaykrishnan Narayanan Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).128 – 133
Li, K. Ma, S. George, J. Sampson and V. Narayanan.Enabling Internet-of-Things: Opportunities brough by emerging devices, circuits and architectures. DATE 2017.
Kaisheng Ma, Xueqing Li, Srivatsa Rangachar Srinivasa, Yongpan Liu, John Sampson, Yuan Xie, Vijaykrishnan Narayanan. Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors. ASP-DAC 2017: 678-683
Shukla, W.Y-. Tsai, M. Jerry, M. Barth, V. Narayanan, S. Datta, “Ultra-low powered coupled oscillators for computer vision applications” VLSI Symposium, Hawaii, June 2016.
Jerry, W. Tsai, B. Xie, X. Li, V. Narayanan, A. Raychodhury and S. Datta, “Phase Transition Oxide Neuron for Spiking Neural Networks” Device Research Conference (DRC), University of Delaware, 2016
Shukla, S. Datta, A. Parihar, V. Narayanan, A. Raychowdhury, “Computing with Dynamical Systems”, Cellular Nanoscale Networks and their Applications, Dresden, 2016.
Sumitha George, Kaisheng Ma, Ahmedullah Aziz, Xueqing Li, Asif Khan, Sayeef Salahuddin, Meng-Fan Chang, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan: Nonvolatile memory design based on ferroelectric FETs. DAC 2016: 118:1-118:6
Danni Wang, Sumitha George, Ahmedullah Aziz, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta: Ferroelectric Transistor based Non-Volatile Flip-Flop. ISLPED 2016: 10-15
Sumitha George, Ahmedullah Aziz, Xueqing Li, Moon Seok Kim, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan: Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors. ISVLSI 2016: 649-654
Wei-Yu Tsai, Davis Barch, Andrew Cassidy, Michael DeBole, Alexander Andreopoulos, Bryan Jackson, Myron Flickner, Dharmendra Modha, Jack Sampson and Vijaykrishnan Narayanan. LATTE: Low-power Audio Transform with TrueNorth Ecosystem. IJCNN 2016.
Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan: A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. ASP-DAC 2015: 118-123
Kevin M. Irick, Peter A. Zientara, Jack Sampson, Vijaykrishnan Narayanan: Cognitive cameras: Assistive vision systems. CASES 2015: 188
Mi Sun Park, Omesh Tickoo, Vijaykrishnan Narayanan, Mary Jane Irwin, Ravi Iyer: Platform-aware dynamic configuration support for efficient text processing on heterogeneous system. DATE 2015: 1503-1508
Siddharth Advani, Brigid Smith, Yasuki Tanabe, Kevin M. Irick, Matthew Cotter, Jack Sampson, Vijaykrishnan Narayanan: Visual co-occurrence network: using context for large-scale object recognition in retail. ESTImedia 2015: 1-10
Siddharth Advani, Yasuki Tanabe, Kevin M. Irick, Jack Sampson, Vijaykrishnan Narayanan: A scalable architecture for multi-class visual object detection. FPL 2015: 1-8
Nandhini Chandramoorthy, Giuseppe Tagliavini, Kevin M. Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini: Exploring architectural heterogeneity in intelligent vision systems. HPCA 2015: 1-12
Kaisheng Ma, Yang Zheng, Shuangchen Li, Karthik Swaminathan, Xueqing Li, Yongpan Liu, Jack Sampson, Yuan Xie, Vijaykrishnan Narayanan: Architecture exploration for ambient energy harvesting nonvolatile processors. HPCA 2015: 526-537
Kaisheng Ma, Xueqing Li, Yongpan Liu, John Sampson, Yuan Xie, Vijaykrishnan Narayanan: Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile. ICCAD 2015: 670-675
Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan: Exploring memory controller configurations for many-core systems with 3D stacked DRAMs. ISQED 2015: 565-570
Moon Seok Kim, William Cane-Wissing, Jack Sampson, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta: Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs. ISVLSI 2015: 303-308
Ahmedullah Aziz, William Cane-Wissing, Moon Seok Kim, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta: Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective. ISVLSI 2015: 333-338
Kaisheng Ma, Nandhini Chandramoorthy, Xueqing Li, Sumeet Kumar Gupta, John Sampson, Yuan Xie, Vijaykrishnan Narayanan: Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing. ISVLSI 2015: 339-344
Karthik Swaminathan, Jagadish Kotra, Huichu Liu, Jack Sampson, Mahmut T. Kandemir, Vijaykrishnan Narayanan: Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures. VLSI Design 2015: 221-226
Unsuk Heo, Xueqing Li, Huichu Liu, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan: A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications. VLSI Design 2015: 304-309
Xiao, C. Zhang, K.M. Irick, J. Sampson and V. Narayanan, “A Task-Oriented Vision System”, in Great Lakes Symposium of VLSI Design (GLSVLSI’14), 2014
Cotter, Y. Fang, D.M. Chiarulli, S.P. Levitan, V. Narayanan, “Computational Architecture Based on Coupled Oscillators”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2014.
Advani, N. Chandramoorthy, K. Swaminathan, K.M. Irick, Y. Cho, J. Sampson and V. Narayanan, “Refresh Enabled Video Analytics: Implications on Power and Performance of DRAM Supported Embedded Visual Systems” in The 32nd IEEE International Conference on Computer Design (ICCD), Oct. 2014
Cotter, S. Advani, J. Sampson, K.M. Irick, V. Narayanan, “A Hardware Accelerated Multilevel Visual Classifier for Embedded Visual Assist Systems”, in International Conference on Computer Aided Design”, 2014.
Park, O. Tickoo, V. Narayanan, C. L. Giles, M. Irwin, R. Iyer, “End-to-End Personal Analytics System for User-friendly Query Processing”, in The 51th ACM/EDAC/IEEE Design Automation Conference (DAC’14), June 2014.
S. Lee, K.M. Irick, J. Sampson, C. Zhang, V. Narayanan, “Exploiting Natural Redundancy in Visual Information” in IEEE International Conference on Computer Design (ICCD), Oct 2014
Huichu Liu, M. Shoaran, X. Li, S. Datta, A. Schmid, V. Narayanan, “Tunnel FET-Based Ultra-Low Power, Low-Noise Amplifier Design for Bio-signal Acquisition”, in proceedings of 2014 IEEE International Symposium on Low Power Electronics and Design (ISLPED’14), pp. 57-62, La Jolla, CA, Aug. 2014. (23% Acceptance Rate).
Swaminathan, Huichu Liu, J. Sampson and V. Narayanan, “An Examination of the Architecture and System-level Tradeoffs of Employing Steep Slope Devices in 3D CMPs”, in International Symposium of Computer Architecture (ISCA’14), pp. 241 – 252, Minneapolis, MN, June, 2014. (17% Acceptance Rate (46/258))
Swaminathan, Huichu Liu, X. Li, M. Kim, J. Sampson and V. Narayanan, “Steep Slope Devices: Enabling New Architectural Paradigms”, in IEEE/ACM Design Automation Conference (DAC’14), pp. 1- 6, San Francisco, CA, June, 2014.
Li, Huichu Liu, K. Ma, U. Heo, S. Datta, V. Narayanan, “RF-Powered Systems Using Steep Slope Devices”, in 12th IEEE International NEWCAS Conference (NEWCAS’14), 4 pages, June 22 – 25, 2014.
Ma, Huichu Liu, Y. Xiao, Y. Zheng, S. Gupta, Y. Xie and V. Narayanan, “IndependentlyControlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed”, in IEEE Computer Society Annual Symposium on VLSI 2014 (ISVLSI’14), 6 pages, July 9-11, 2014.
S. Kim, Huichu Liu, K. Swaminathan, X. Li, S. Datta, V. Narayanan, “Enabling Power-Efficient Designs with III-V Tunnel FETs” (invited), in 2014 IEEE Compound Semiconductor IC Symposium (CSICS’14), 6 pages, San Diego, California, Oct. 19-22, USA,
-Y. Tsai, Huichu Liu, X. Li and V. Narayanan, “Low-power High-Speed Current Mode Logic using Tunnel-FET”, 22nd IFIP/IEEE International Conference on Very Large Scale Integration, (VLSI-SoC’14), 6 pages, Oct 6, 2014 – Oct 8
Barth, Huichu Liu, Z. Yuan, A. Kumar, H. Hughes, P. McMarr, J. Warner, J.B. Boos, E. X. Zhang, C. X. Zhang, D. McMorrow, B.R. Bennett, V. Narayanan, S.Datta and K.C. Saraswat “Total-Ionizing Dose Mechanisms in Antimony (Sb)-based CMOS Transistors with High-κ Dielectric”, in 39th Annual GOMACTech’14, 2 pages, 31 March – 3 April 2014.
Li, W.-Y. Tsai, Huichu Liu, S. Datta and V. Narayanan, “A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET”, in IEEE Computer Society Annual Symposium on VLSI 2014 (ISVLSI’14), 6 pages, July 9-11, 2014.
Karthik Swaminathan, Moon Seok Kim, Nandhini Chandramoorthy, Behnam Sedighi, Robert Perricone, Jack Sampson and Vijaykrishnan Narayanan, “Modeling Steep Slope Devices: From Circuits to Architectures” in Design Automation and Testing in Europe (DATE’14), pp. 1 – 6, Dresden, Germany, Mar, 2014.
Nandhini Chandramoorthy, Karthik Swaminathan, Matthew Cotter, Xueqing Li, Indranil Palit, Kevin Irick, Sharon Hu, Michael Niemier and Vijaykrishnan Narayanan, “Understanding the landscape of accelerators for vision,” 6 pages, 2014 IEEE International Workshop on Signal Processing Systems
Shukla, A. Parihar, M. Cotter, M. Barth, X. Li, N. Chandrammorthy, D. G. Schlom, V. Narayanan, A. Raychowdhury and S. Datta, “Pairwise coupled hybrid vanadium dioxide-MOSFET (HVFET) oscillators for non-boolean associative computing,” 3 pages, IEDM 2014
Melvin Eze, Ozcan Ozturk, Vijaykrishnan Narayanan: Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect. VLSI-SoC 2013: 296-301, October 2013
Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Jürgen Teich: Run-time adaption for highly-complex multi-core systems. CODES+ISSS 2013: 1-8 October 2013
Huichu Liu, Suman Datta, Vijaykrishnan Narayanan: Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications. ISLPED 2013: 145-150, September 2013
Huichu Liu, Ramesh Vaddi, Suman Datta, Vijaykrishnan Narayanan: Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier. ISLPED 2013: 157-162, September 2013
Park, C. Zhang, M. DeBole, S. Kestur, V. Narayanan, M. Irwin, “Accelerators for Biologically-Inspired Attention and Recognition”, To appear in Proc. of the 50th ACM/EDAC/IEEE Design Automation Conference, Austin, USA, June 2013.
Jia Zhan, Nikolay Stoimenov, Jin Ouyang, Lothar Thiele, Vijaykrishnan Narayanan, Yuan Xie: Designing energy-efficient NoC for real-time embedded systems through slack optimization. DAC 2013: 37, June 2013
Siddharth Advani, John P. Sustersic, Kevin M. Irick, Vijaykrishnan Narayanan: A multi-resolution saliency framework to drive foveation. ICASSP 2013: 2596-2600, May 2013
Nandhini Chandramoorthy, Siddharth Advani, Kevin M. Irick, Vijaykrishnan Narayanan: A Configurable Architecture for a Visual Saliency System and Its Application in Retail. FCCM 2013: 233, April 2013
Chuanjun Zhang, Glenn G. Ko, Jungwook Choi, Shang-nien Tsai, Minje Kim, Abner Guzmán-Rivera, Rob A. Rutenbar, Paris Smaragdis, Mi Sun Park, Vijaykrishnan Narayanan, Hongyi Xin, Onur Mutlu, Bin Li, Li Zhao, Mei Chen: EMERALD: Characterization of emerging applications and algorithms for low-power devices. ISPASS 2013: 122-123. April 2013
Datta, R. Bijesh, H. Liu, D. Mohata, and V. Narayanan “Tunnel Transistors for Energy Efficent Computing” IEEE International Reliability Physics Symposium (IRPS),Monterey, California, April 14- 18 2013
Liu, M. Cotter, V. Narayanan and S. Datta, “Evaluation Soft Error Rate Immunity in Emerging Devices”, GOMACTech 2013, March 2013.
Yang Xiao, Kevin M. Irick, Vijaykrishnan Narayanan, Donghwa Shin, Naehyuck Chang: Saliency aware display power management. DATE 2013: 1203-1208, March 2013
Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan: On reconfigurable single-electron transistor arrays synthesis using reordering techniques. DATE 2013: 1807-1812, March 2013
Matthew Cotter, Huichu Liu, Suman Datta, Vijaykrishnan Narayanan: Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications. ISQED 2013: 430-437, March 2013
Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Matthew Poremba, Vijaykrishnan Narayanan, Yuan Xie, Chung-Ta King: TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network. HPCA 2013: 390-399, Feb 2013
Yuan-Ying Chang, Yoshi Shih-Chieh Huang, Vijaykrishnan Narayanan, Chung-Ta King: ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise. ASP-DAC 2013: 675-680, January 2013
Liu*, H., M. Cotter*, S. Datta, N. Vijaykrishnan. December 2012. Technology Assessment of Si and III-V FinFETs and III-V Tunnel FETs From Soft Error Rate Perspective. Proceedings of the IEEE International Electron Devices Meeting (IEDM 2012). pp. 577-580. San Francisco, CA. (First two authors supervised by candidate)
Cho*, Y., N. Chandramoorthy*, K. Irick, N. Vijaykrishnan. October 2012. Multiresolution Gabor Feature Extraction for Real Time Applications. Proceedings of the 2012 IEEE Workshop on Signal Process Systems (SIPS 2012). pp. 55-60. Quebec City, Quebec, Canada. (First two authors supervised by candidate)
Kultursay, E., K. Swaminathan*, V. Saripalli*, N Vijaykrishnan, M. Kandemir, S. Datta. October 2012. Performance Enhancement Under Power Constraints Using Heterogeneous CMOS-TFET Multicores. Proceedings of the Tenth International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2012). pp. 245-254. Tampere, Finland. (Second author supervised and third author co-supervised by candidate) (Best paper nomination)
Mukundrajan*, R., M. Cotter*, V. Saripalli*, M. J. Irwin, S. Datta, N. Vijaykrishnan. August 2012. Ultra Low Power Circuit Design Using Tunnel FETs. Proceedings of the IEE Computer Society Annual Symposium on VLSI (ISVLSI 2012). pp. 153-158. Amherst, MA. (First author supervised and second and third authors co-supervised by candidate)
Swaminathan*, K., E. Kultursay, V. Saripalli*, N. Vijaykrishnan, M. Kandemir. July 30-August 1, 2012. Design Space Evaluation of Workload-specified Last Level Caches. Proceedings of the International Symposium on Low Power Electronics Design (ISLPED 2012). pp. 243-248. Redondo Beach, CA. (First author supervised and third author co-supervised by candidate)
Liu*, H., D. Mohata, A. Nidhi, V. Saripalli*, N. Vijaykrishnan, S. Datta. June 2012. Exploration of Vertical MOSFET and Tunnel FET Device Architecture for Sub 10nm Node Applications. Proceedings of the Seventieth Annual Device Research Conference (DRC 2012). pp. 233-234. University Park, PA. (First and fourth authors supervised by candidate)
Agrawal, N. V. Saripalli*, N. Vijaykrishnan, Y. Kumura, R. Arghavani, S. Datta. June 2012. Will Strong Quantum Confinement Effect Limit Low VCC Logic Application of III-V FinFETs? Proceedings of the Seventieth Annual Device Research Conference (DRC 2012). University Park, PA. (Second author supervised by candidate)
Mohata, D., R. Bijesh, Y. Zhu, M. K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J. M. Fastenau, D. Loubychev, A. K. Liu, T. S. Mayer, N. Vijaykrishnan, S. Datta. June 2012. Demonstration of Improved Heteroepitaxy, Scaled Gate Stack and Reduced Interface States Enabling Heterojunction Tunnel FETs with Hihg Drive Current and High On-Off Ratio. Proceedings of the IEEE Symposia on VLSI Technology and Circuits. pp. 53-54. Honolulu, HI.
Al-Maashri*, A. M. DeBole, M. Cotter*, N. Chandramoorthy*, Y. Xiao*, N. Vijaykrishnan, C. Chakrabarti. June 2012. Accelerating Neuromorphic Vision Algorithms for Recognition. Proceedings of the Forty-Ninth Annual Design Automation Conference (DAC 2012). 579-584. San Francisco, CA. (First, third, and fifth authors supervised and fourth author co-supervised by candidate)
Jog, A., A. Mishra, C. Xu, Y. Xie, N. Vijaykrishnan, R. Iyer, C. R. Das. June 2012. Cache Revive: Architecting Volatile STT-RAM Caches for Enhanced Performance in CMPs. Proceedings of the Forty-Ninth Annual Design Automation Conference (DAC 2012). 243-252. San Francisco, CA.
Xie*, J., N. Vijaykrishnan, Y. Xie. May 2012. Mitigating Electromigration of Power Supply Networks using Bidirectional Current Stress. Proceedings of the Great Lakes Symposium on VLSI (GLVLSI 2012). 299-302. Salt Lake City, UT. (First author supervised by candidate)
Kestur*, S., S.-M. Park*, J. Sabarad*, D. Dantara*, N. Vijaykrishnan, Y. Chen, D. Khosla. April 29-May 1, 2012. Emulating Mammalian Vision on Reconfigurable Hardware. Proceedings of the IEEE Twentieth Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2012). 141-148. Toronto, Ontario, Canada. (First author co-supervised and second, third, and fourth authors supervised by candidate)
Park*, S.-M., S. Kestur*, J. Sabarad*, N. Vijaykrishnan, M. J. Irwin. March 2012. An FPGA-based Accelerator for Cortical Object Classification. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2012). 691-696. Dresden, Germany. (First and third author supervised and second author co-supervised by candidate)
Singh, P., N. Vijaykrishnan, D. Landis. March 2012. Hazard Driven Test Generation for SMT Processors. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE 2012). 256-259. Dresden, Germany.
Sabarad*, J. S. Kestur*, S.-M. Park*, D. Dantara*, N. Vijaykrishnan, Y. Chen, D. Khosla. January 30-February 2, 2012. A Reconfigurable Accelerator for Neuromorphic Object Recognition. Proceedings of the Seventeenth Asia and South Pacific Design Automation Conference (ASP-DAC 2012). pp. 813-818. Sydney, Australia. (First four authors supervised by candidate)
Swaminathan*, K. R. Pisolkar, C. Xu, N. Vijaykrishnan. January 30-February 2, 2012. When to Forget: A System-level Perspective on STT-RAMs. Proceedings of the Seventeenth Asia and South Pacific Design Automation Conference (ASP-DAC 2012). pp. 311-316. Sydney, Australia. (First author supervised by candidate)
Park*, S., Y. Cho*, K. Irick, N. Vijaykrishnan. January 30-February 2, 2012. A Reconfigurable Platform for the Design and Verification of Domain-specific Accelerators. Proceedings of the Seventeenth Asia and South Pacific Design Automation Conference (ASP-DAC 2012). pp. 108-113. Sydney, Australia. (First two authors supervised by candidate)
Liu, L., V. Saripalli*, N. Vijaykrishnan, S. Datta. December 2011. Device Circuit Co-Design Using Classical and Non-Classical III-V Multi-Gate Quantum-Well FETs (MuQFETs). Proceedings of the 2011 IEEE International Electron Devices Meeting (IEDM). 4 pages. Washington, D.C. (Second author co-supervised by candidate)
Mohata, D. K., R. Bijesh, S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, N. Vijaykrishnan, J. Fastenau, D. Loubychev, A. Liu, S. Datta. December 2011. Demonstration of MOSFET-Like On-Current Performance in Arsenide/ Antimonide Tunnel FETs with Staggered Hetero-junctions for 300mV Logic Applications. Proceedings of the 2011 IEEE International Electron Devices Meeting (IEDM). 4 pages. Washington, D.C.
DeBole, M., C-L Yu, A. Al Maashri, M. Cotter, C. Chakrabarti, V. Narayanan. November 2011. FPGA-Accelerator System for Computing Biologically-Inspired Feature Extraction Models. Asilomar Conference on Signals, Systems, and Computers.
DeBole, M., Al Maashri, M. Cotter, C-L Yu, C. Chakrabarti, V. Narayanan. November 2011. A Framework for Accelerating Neuromorphic-Vision Algorithms on FPGAs. IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2011).
Al Maashri, A., M. DeBole, C.-L. Yu, V. Narayanan, C. Chakrabarti. October 2011. A Hardware Architecture for Accelerating Neuromorphic Vision Algorithms. IEEE Workshop on Signal Processing Systems (SiPS 2011). October 2011.
Cho, Y, Bae, Y. Jin, K. M. Irick, V. Narayanan. September 2011. Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA. FPL 2011: 311-316
Swaminathan K., E. Kultursay, V. Saripalli, V. Narayanan, M. Kandemir and S. Datta, August 2011 Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores International Symposium on Low Power Electronics and Design (ISLPED).
Swaminathan, K., Mukundrajan, N. Soundararajan, V. Narayanan. July 2011. Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM. ISVLSI 2011: 236-241
Chen, H-W, Srinivasan, Y. Xie, V. Narayanan. July 2011. Impact of Circuit Degradation on FPGA Design Security. ISVLSI 2011: 230-235
Park, S., S. Kestur, K. M. Irick and V. Narayanan. Accelerating Neuromorphic Vision on FPGAs. Embedded Computer Vision Workshop (in Conjunction with CVPR) (Invited)
Saripalli, V., J. P. Kulkarni, N. Vijaykrishnan and S. Datta, June 2011. Variation-Tolerant Ultra Low-Power Heterojunction Tunnel FET SRAM Design”, IEEE/ACM Intl. Symp. on Nanoscale Architectures (NanoArch).
Mishra, A. K., Dong, G. Sun, Y. Xie, N. Vijaykrishnan, C. R. Das. June 2011 Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. ISCA 2011: 69-80
Mishra, A. K, N. Vijaykrishnan, R. Das. June 2011. A case for heterogeneous on-chip interconnects for CMPs. ISCA 2011: 389-400
Kestur, S., M. Irick, S. Park, A. Al-Maashri, V. Narayanan, C. Chakrabarti: June 2011. An algorithm-architecture co-design framework for gridding reconstruction using FPGAs. IEEE/ACM Design Automation Conference DAC 2011: 585-590
Saripalli, V., A. K. Mishra, N. Vijaykrishnan and S. Datta. June 2011. An Energy-Efficient Heterogeneous CMP based on Hybrid TFET-CMOS Cores”, IEEE/ACM Design Automation Conference (DAC).
Chen, Y-C, Eachempati, C-Y Wang, S. Datta, Y. Xie, V. Narayanan. June 2011. Automated mapping for reconfigurable single-electron transistor arrays. IEEE/ACM Design Automation Conference DAC 2011: 878-883
Liu, L., V. Saripalli, V. Narayanan and S. Datta, June 2011. Experimental Investigation of Scalability and Transport in In0:7Ga0:3As Multi-Gate Quantum Well FET (MuQFET). 69th Device Research Conference (DRC).
Vijaykrishnan N., Saripalli, K. Swaminathan, R. Mukundrajan, G. Sun, Y. Xie, S. Datta. May 2011. Enabling architectural innovations using non-volatile memory. ACM Great Lakes Symposium on VLSI 2011: 439-444
Bae, S. Cho, S. Park, K M. Irick, Y Jin, V. Narayanan. May 2011. An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization. FCCM 2011: 41-48
Kestur, S , Dantara, V. Narayanan. March 2011. SHARC: A streaming model for FPGA accelerators and its application to Saliency. DATE 2011: 1237-1242
Bae*, S. M., N. Vijaykrishnan. August 2010. Thermal Gradient Aware Clock Skew Scheduling for FPGAs. Proceedings of the Twentieth International Conference on Field Programmable Logic and Applications (FPL 2010). 101-106. Milano, Italy. (First author supervised by candidate)
Sampath* Kumar, V., K. Irick*, A. Al Maashri*, N. Vijaykrishnan. July 2010. A Scalable Bandwidth Aware Architecture for Connected Component Labeling. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010). 116-121. Lixouri Kefalonia, Greece. (First author co-supervised and second and third authors supervised by candidate)
Vijaykrishnan, N., A. Al Mashri*, K. Irick*, M. DeBole*, S. Park*. July 2010. AutoFLEX: A Framework for Image Processing Applications on Multi-FPGA Systems. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2010). 59-66. Las Vegas, NV. (Second, third, and fifth authors supervised and fourth author co-supervised by candidate) (Invited)
Soundararajan*, N., A. Sivasubramaniam, N. Vijaykrishnan. June 2010. Characterizing Soft-error Vulnerability of Mulicores Running Multi-threaded Applications. Proceedings of the ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS 2010). 379-380. New York, NY. (First author co-supervised by candidate) (Poster)
Saripalli*, V., D. K. Mohata, S. Mookerjea, S. Datta, N. Vijaykrishnan. June 2010. Low Power Loadless 4T SRAM Cell Based on Degenerately Doped Source (DDS) In_0.53 GA_0.47 as Tunnel FETs. Proceedings of the IEEE Device Research Conference (DRC 2010). 101-102. (First author co-supervised by candidate)
Datta, S., A. Ali, S. Mookerjea, V. Saripalli*, L. Liu, S. Eachempati, T. Mayer, N. Vijaykrishnan. , June 2010. “Non-silicon Logic Elements on Silicon for Extreme Voltage Scaling,” Proceedings of the Silicon Nanoelectronics Workshop (SNW), pp.15-16, Honolulu, Hawaii.
Liu, L., V. Saripalli, E. Hwang, V. Narayanan and S. Datta. May 2011. Multi-Gate Modulation Doped In0.7Ga0.3As Quantum Well FET for Ultra Low Power Digital Logic. 219th Electro chemical Society (ECS) Meeting.
Kestur*, S., S. Park*, K. Irick*, N. Vijaykrishnan. May 2010. Accelerating the Nonuniform Fast Fourier Transform Using FPGAs. Proceedings of the Eighteenth IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2010). 19-26. Charlotte, NC. (First author co-supervised and second and third authors supervised by candidate)
Kandemir, M., O. Ozturk, S. Narayanan, M. J. Irwin. April 2010. Compiler Directed Communication Reliability Enhancement for Chip Multiprocessors. Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES 2010). 85-94. Stockholm, Sweden.
Yu, C.-L., C. Chakrabarti, S. Park*, N. Vijaykrishnan. March 2010. Bandwidth-intensive FPGA Architecture for Multi-dimensional DFT. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2010). 1486-1489. Dallas, TX. (Third author supervised by candidate)
Ricketts*, A., N. Vijaykrishnan, J. Singh*, D. Pradhan. March 2010. Investigating the Impact of NBTI on Different Power Saving Cache Strategies. Proceedings of the Design, Automation & Test in Europe (DATE 2010). 592-597. Dresden, Germany. (First and third authors supervised by candidate)
Rathi*, A., M. DeBole*, W. Ge, R. Collins, N. Vijaykrishnan. March 2010. A GPU Based Implementation of Center-Surround Distribution Distance for Feature Extraction and Matching. Proceedings of the Design, Automation & Test in Europe (DATE 2010). pp. 172-177. Dresden, Germany. (First two authors co-supervised by candidate)
Yanamandra*, A., S. Eachempati*, N. Soundararajan*, N. Vijaykrishnan, M. J. Irwin, R. Krishnan*. January 2010. Optimizing Power and Performance for Reliable On-Chip Networks. Proceedings of the Fifteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2010). 431-436. Taipei, Taiwan. (First, second, third, and sixth authors co-supervised by candidate)
Singh, J., R. Krishnan*, S. Mookerjea, S. Datta, N. Vijaykrishnan. January 2010. A Novel Si-Tunnel FET based SRAM Design for Ultra Low-Power 0.3V VDD Applications. Proceedings of the Fifteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2010). 181-186. Taipei, Taiwan. (Second author co-supervised by candidate)
Saripalli*, V., N. Vijaykrishnan, S. Datta. January 2010. Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors. Proceedings of the Twenty-Third International Conference on VLSI Design (VLSI Design 2010). 399-404. Bangalore, India. (First author co-supervised by candidate)
Mookerjea, S., D. Mohata, R. Krishnan*, J. Singh*, A. Vallett, A. Ali, T. Mayer, N. Vijaykrishnan, D. Schlom, A. Liu, S. Datta. December 2009. Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications. Proceedings of the IEEE International Electron Devices Meeting (IEDM 2009). 3 pages. Baltimore, MD. (Third author co-supervised and fourth author supervised by candidate)
Mishra, A., R. Das, S. Eachempati*, N. Vijaykrishnan, C. R. Das. December 2009. A Case for Dynamic Frequency Tuning in On-Chip Networks. Proceedings of the Forty-Second International Symposium on Microarchitecture (MICRO-42). 292-303. New York, NY. (Third author co-supervised by candidate)
Saripalli*, V., N. Vijaykrishnan, S. Datta. October 2009. Ultra Low Energy Binary Decision Diagram Circuits using Few Electron Transistors. Proceedings of the Workshop on Nano-Bio Sensing Paradigms and Applications, in conjunction with Nano-Net 2009. 200-209. Luzern, Switzerland. (First author co-supervised by candidate)
Al* Maashri, A., G. Sun, X. Dong, N. Vijaykrishnan, Y. Xie. October 2009. 3D GPU Architecture using Cache Stacking: Performance, Cost, Power, and Thermal Analysis. Proceedings of the International Conference on Computer Design (ICCD 2009). 254-259. Lake Tahoe, CA. (First author supervised by candidate)
Kim*, J.S., C.-L. Yu, L. Deng, S. Kestur*, N. Vijaykrishnan, C. Chakrabarti. October 2009. FPGA Architecture for 2D Fast Fourier Transform Based on 2D Decomposition for Large-Sized Data. Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS 2009). 121-126. Tampere, Finland. (First author supervised and fourth author co-supervised by candidate)
Irick*, K., M. DeBole*, S. Park*, N. Vijaykrishnan. August 2009. A Scalable Multi-FPGA Framework for Real-time Digital Signal Processing. Proceedings of SPIE Optics+Photonics Conference. 6 pages. San Diego, CA. (First and third authors supervised and second author co-supervised by candidate)
Datta, S., N. Vijaykrishnan. August 2009. Green Transistors to Green Architectures. Proceedings of the 2009 International Symposium on Low Power Electronics and Design (ISLPED 2009). 429-430. San Francisco, CA.
Xie, Y., S. Eachempati*, A. Yanamandra*, N. Vijaykrishnan, M. J. Irwin. July 2009. Power and Area Reduction using Carbon Nanotube Bundle Interconnect in Global Clock Tree Distribution Network. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2009). pp. 51-56. San Francisco, CA. (Second and third authors co-supervised by candidate)
Bae*, S., R. Krishnan*, N. Vijaykrishnan. May 2009. A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009). 193-198. Tampa, FL. (First author supervised and second author co-supervised by candidate)
Mangalagiri*, P., N. Vijaykrishnan. May 2009. Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2009). 61-66. Tampa, FL. (First author co-supervised supervised by candidate)
Bae*, S., P. Mangalagiri*, N. Vijaykrishnan. April 2009. Exploiting Clock Skew Scheduling for FPGA. Proceedings of the Design Automation & Test in Europe (DATE 2009). 1524-1529. Nice, France. (First author supervised and second author co-supervised by candidate)
Das, R., S. Eachempati*, A. K. Mishra, N. Vijaykrishnan, C. R. Das. February 2009. Design and Evaluation of a Hierarchical On-Chip Interconnect for Next-Generation CMPs. Proceedings of the Fifteenth International Symposium on High-Performance Computer Architecture (HPCA-15). 175-186. Raleigh, NC. (Second author co-supervised by candidate)
Yanamandra*, A., M. J. Irwin, N. Vijaykrishnan, M. Kandemir, S. H. K. Narayanan. January 2009. In-Network Caching for Chip Multiprocessors. Proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2009). Springer-Verlag LNCS 5409:373-388. Paphos, Cyprus. (First author co-supervised by candidate)
Sridharan*, S., M. DeBole*, G. Sun, Y. Xie, N. Vijaykrishnan. January 2009. A Criticality-Driven Microarchitectural Three Dimensional (3D) Floorplanner. Proceedings of the Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2009). 763-768. Yokohama, Japan. (First author supervised and second author co-supervised by candidate)
DeBole*, M., R. Krishnan*, V. Balakrishnan, W. Wang, L. Hong, Y. Wang, Y. Xie, Y. Cao, N. Vijaykrishnan. January 2009. A Framework for Estimating NBTI Degradation of Microarchitectural Components. Proceedings of the Fourteenth Asia and South Pacific Design Automation Conference (ASP-DAC 2009). 455-460. Yokohama, Japan. (First two authors co-supervised by candidate)
Henkel, J., N. Vijaykrishnan, S. Parameswaran, R. Ragel. January 2009. Security and Dependability of Embedded Systems: A Computer Architects’ Perspective. Proceedings of the Twenty-Second International Conference on VLSI Design (VLSI Design 2009). 30-32. New Delhi, India.
Mangalagiri*, P., S. Bae*, R. Krishnan*, N. Vijaykrishnan, Y. Xie, T. Tuan. November 2008. Thermal-Aware Reliability Analysis for Platform FPGAs. Proceedings of the International Conference on Computer Aided Design (ICCAD 2008). 722-727. San Jose, CA. (First two authors supervised and third author co-supervised by candidate)
Ramakrishnan*, K., N. Vijaykrishnan, Y. Xie. October 2008. Comparative Analysis of NBTI Effects on Low Power and High Performance Flip-Flops. Proceedings of the XXVI International Conference on Computer Design (ICCD 2008). 200-208. Lake Tahoe, CA. (First author supervised by candidate)
Deng, L., C-L. Yu, C. Chakrabarti, J. Kim*, N. Vijaykrishnan. October 2008. Efficient Image Reconstruction Using Partial 2D Fourier Transform. Proceedings of the 2008 IEEE Workshop on Signal Processing Systems (SIPS 2008). pp. 49-54. Washington, D.C.
Soundararajan, N., N. Vijaykrishnan, A. Sivasubramaniam. August 2008. Impact of DVFS on the Architectural Vulnerability of GALS Architctures. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2008). 351-356. Bangalore, India.
Soundararajan, N., A. Yanamandra, C. Nicopoulos*, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin. June 2008. Analysis and Solutions to Issue Queue Process Variation. Proceedings of the Thirty-Eighth Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2008). 11-21. Anchorage, Alaska. (Third author supervised by candidate)
Park, D., S. Eachempati*, R. Das, A. K Mishra, N. Vijaykrishnan, Y. Xie, C. R Das. June 2008. MIRA: A Multi-Layered On-Chip Interconnect Router Architecture. Proceedings of the International Symposium on Computer Architecture (ISCA 2008). 251-261. Beijing, China. (Second author supervised by candidate)
Eachempati*, S., V. Saripalli*, N. Vijaykrishnan, S. Datta. June 2008. Reconfigurable BDD Based Quantum Circuits. Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch 2008). pp. 61-67. Anaheim, CA. (First author supervised and second author co-supervised by candidate)
Mangalagiri*, P., K. Sarpatwari, A. Yanamandra, N. Vijaykrishnan, Y. Xie, M. J. Irwin, O. A. Karim. May 2008. A low-power Phase Change Memory Based Hybrid Cache Architecture. Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI 2008). 395-398. Orlando, FL. (First author supervised by candidate)
Irick*, K., N. Vijaykrishnan, M. DeBole*, A. Gayasen*. April 2008. A Hardware Efficient Support Vector Machine Architecture for FPGA. Proceedings of the Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2008). pp. 304-305. Stanford, CA. (First author supervised and third and fourth authors co-supervised by candidate)
Krishnan*, R., R. Ramanarayanan*, N. Vijaykrishnan, Y. Xie, M. J. Irwin, K. Unlu. March 2008. Hierarchical Soft Error Estimation Tool (HSEET). Proceedings of the Ninth International Symposium on Quality Electronic Design (ISQED 2008). 680-683. San Jose, CA. (First author supervised and second author co-supervised by candidate)
Das, R., A. K. Mishra, C. Nicopoulos*, D. Park, N. Vijaykrishnan, R. Iyer, C. R. Das. February 2008. Performance and Power Optimization through Data Compression in Network-on-Chip Architectures. Proceedings of the Fourteenth International Symposium on High Performance Computer Architecture (HPCA 2008). 215-225. Salt Lake City, UT. (Third author supervised by candidate)
Atienza, D., G. De Micheli, L. Benini, J. L. Ayala, P. G. Del Valle, M. DeBole*, N. Vijaykrishnan. January 2008. Reliability-Aware Design for Nanometer-Scale Devices. Proceedings of the Thirteenth IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC 2008). 549-554. Seoul, Korea. (Sixth author co-supervised by candidate)
Irick*, K., M. DeBole*, N. Vijaykrishnan, R. Sharma, H. Moon, S. Mummareddy. August 2007. A Unified Streaming Architecture for Real Time Face Detection and Gender Classification. Proceedings of the Seventeenth International Conference on Field Programmable Logic and Applications (FPL 2007). 267-272. Amsterdam, Netherlands. (First author supervised and second author co-supervised by candidate)
Kim*, J., P. Mangalagiri*, K. Irick*, M. Kandemir, N. Vijaykrishnan, K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, X. Sun. August 2007. TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform. Proceedings of the Seventeenth International Conference on Field Programmable Logic and Applications (FPL 2007). 68-73. Amsterdam, Netherlands. (First three authors supervised by candidate)
Park, D., R. Das, C. Nicopoulos*, J. Kim, N. Vijaykrishnan, R. Iyer, C. R. Das. August 2007. Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Proceedings of the Fifteenth Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007). 15-20. Stanford, CA. (Third author supervised by candidate)
Kim, J., C. Nicopoulos*, D. Park, R. Das, Y. Xie, N. Vijaykrishnan, C. R. Das. June 2007. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. Proceedings of the Thirty-Fourth Annual International Symposium on Computer Architecture (ISCA 2007). 138-149. San Diego, CA. (Second author supervised by candidate)
Ricketts*, A., M. Mutyam*, N. Vijaykrishnan, M. J. Irwin. May 2007. Investigating Simple Low Latency Reliable Multiported Register Files. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007). 375-382. Porte Alegre, Brazil. (First two authors supervised by candidate)
Mondal, M., A. Ricketts*, S. Kirolos, T. Ragheb, G. Link, N. Vijaykrishnan, Y. Massoud. April 2007. Thermally Robust Clocking Schemes for 3D Integrated Circuits. Proceedings of the Design, Automation and Test in Europe (DATE’07). 1206-1211. Nice, France. (Second author supervised by candidate)
Mutyam*, M., N. Vijaykrishnan. April 2007. Working with Process Variation Aware Caches. Proceedings of the Design, Automation and Test in Europe (DATE’07). 1152-1157. Nice, France. (First author supervised by candidate)
Eachempati*, S., A. Nieuwoudt, A. Gayasen, Y. Massoud, N. Vijaykrishnan. April 2007. Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. Proceedings of the Design, Automation and Test in Europe (DATE’07). 307-312. Nice, France. (First author supervised)
Krishnan*, R., R. Ramanarayanan*, S. Srinivasan*, N. Vijaykrishnan, Y. Xie, M. J. Irwin. March 2007. Variation Impact on SER of Combinational Circuits. Proceedings of the International Society for Quality Electronic Design (ISQED 2007). 911-916. San Jose, CA. (First and third author supervised and second author co-supervised by candidate)
Mupid*, A., M. Mutyam*, N. Vijaykrishnan, Y. Xie, M. J. Irwin. March 2007. Variation Analysis of CAM Cells. Proceedings of the Eighth International Symposium on Quality Electronic Design (ISQED 2007). 333-338. San Jose, CA. (First two authors supervised by candidate)
Mondal, M., A. Ricketts*, S. Kirolos, T. Ragheb, G. Link, N. Vijaykrishnan, Y. Massoud. March 2007. Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. Proceedings of the International Society for Quality Electronic Design (ISQED 2007). 67-72. San Jose, CA. (Second author supervised)
Ramakrishnan*, R S. Srinivasan*, N. Vijaykrishnan, Y. Xie. January 2007. Impact of NBTI on FPGAs. Proceedings of the International Conference on VLSI Design. 717-722. Bangalore, India. (First and second authors supervised by candidate) (141 papers accepted out of 444 submissions) (32% acceptance rate)
Vaidyanathan, B., W. Hung, F. Wang, Y. Xie, N. Vijaykrishnan, M. J. Irwin. January 2007. Architecting Microprocessor Components in 3D Design Space. Proceedings of the Twentieth International Conference on VLSI Design. 103-108. Bangalore, India. (141 papers accepted out of 444 submissions) (32% acceptance rate)
Nicopoulos*, C. A., D. Park, J. Kim, N. Vijaykrishnan, C. R. Das. December 2006. ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. Proceedings of the International Symposium on Microarchitecture (MICRO 06). pp. 333-346. Orlando, FL. (First author supervised by candidate) (42 papers accepted out of 174 submissions) (24% acceptance rate)
Vaidyanathan, B., Y. Xie, N. Vijaykrishnan, R. Luo. December 2006. Leakage Optimized DECAP Design for FPGAs. Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006). 960-963. Singapore.
Sundararajan*, P. A. Gayasen*, N. Vijaykrishnan, T. Tuan. November 2006. Thermal Characterization and Optimization in Platform FPGAs. Proceedings International Conference on Computer Aided Design (ICCAD-2006). pp. 443-447. San Jose, CA. (First author supervised and second author co-supervised by candidate) (130 papers accepted out of 537 submissions) (24% acceptance rate)
Sundararajan*, P, S. Krishnamurthy, N Vijaykrishnan, K. Chaudhary, R. Jayaraman. September 2006. Performance Improvements Through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs. Proceedings of the IEEE International System on Chip Conference (SOCC 2006). pp. 105-106. Austin, TX. (First author supervised by candidate)
Chen, G, L. Xue, J. Kim*, K. Sobti, L. Deng, X. Sun, N. Pitsianis, C. Chakrabarti, M. Kandemir, N. Vijaykrishnan. September 2006. Using Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations. Proceedings of the IEEE International System on Chip Conference (SOCC 2006). 113-114. Austin, TX. (Third author supervised by candidate)
Srinivasan*, S., R. Ramadoss*, N. Vijaykrishnan. September 2006. Process Variation Aware Parallelization Strategies for MPSoCs. Proceedings of the IEEE International System on Chip Conference (SOCC 2006). 179-184. Austin, TX. (First and second author supervised by candidate)
Park, D., C. Nicopoulos*, J. Kim, N. Vijaykrishnan, C. R. Das. September 2006. A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects. Proceedings of the First International Conference on Nano-Networks (Nano-Net 2006). CDROM proceedings. 6 pages. Lausanne, Switzerland. (Second author supervised by candidate)
Srinivasan*, S., M. Prasanth*, S. Karthink, Y. Xie, N. Vijaykrishnan. July 2006. FLAW: FPGA Lifetime Awareness. Proceedings of the Forty-Third Design Automation Conference (DAC 2006). 630-635. San Francisco, CA. (First two authors supervised by candidate) (accepted 209 out of 865 submissions) (24% acceptance rate)
Park, D., C. A. Nicopoulos*, J. Kim, N. Vijaykrishnan, C. R. Das. June 2006. Exploring Fault-Tolerant Network-on-Chip Architectures. Proceedings of the International Conference on Dependable Systems and Networks – DCCS Track (DSN-2006). pp. 93-102. Philadelphia, PA. (Second author supervised by candidate) (34 papers accepted out of 187 submissions) (19% acceptance rate)
Li, F., C. Nicopoulos*, T. Richardson, Y. Xie, N. Vijaykrishnan, M. Kandemir. June 2006. Design and Management of 3D Chip Multiprocessors using Network-in-memory. Proceedings of the Thirty-Third Annual International Symposium on Computer Architecture (ISCA 2006). pp. 130-141. Boston, MA. (Second author supervised by candidate) (31 papers accepted out of 234 submissions) (13% acceptance rate)
Kim, J., C. A. Nicopoulos*, D. Park, N. Vijaykrishnan, C. R. Das. June 2006. A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks. Proceedings of the Thirty-Third Annual International Symposium on Computer Architecture (ISCA 2006). pp. 4-15. Boston, MA. (Second author supervised by candidate) (31 papers accepted out of 234 submissions) (13% acceptance rate)
Mutyam*, M., F. Li, N. Vijaykrishnan, M. Kandemir, M.J. Irwin. June 2006. Compiler Directed Thermal Management for VLIW Functional Units. Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2006). pp. 163-172. Ottawa, Canada. (First author supervised by candidate) (21 accepted out of 83 submissions) (25% acceptance rate)
Gayasen*, A., N. Vijaykrishnan, M. Kandemir, A. Rahman. April 2006. Switch Box Architectures for Three-Dimensional FPGAs. Proceedinsg of the IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). 2 pages. Napa Valley, CA. (First author co-supervised by candidate)
Ramanarayanan*, R., Krishnan*, N. Vijaykrishnan, Y. Xie, M. J. Irwin. April 2006. Temperature and Voltage Scaling Effects on Electrical Masking. Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE 2006). 4 pages. Urbana, IL. (First author co-supervised and second author supervised by candidate)
Vaidyanathan, B., Y. Xie, N. Vijaykrishnan, H. Zheng. April 2006. Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits. Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE 2006). 4 pages. Urbana, IL.
Lin*, I., S. Srinivasan*, N. Vijaykrishnan, N. Dhanwada. March 2006. Transaction Level Error Susceptibility Model for SoC Bus Based SoC Architectures. Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006). pp. 775-780. San Jose, CA. (First author co-supervised and second author supervised by candidate) (93 regular papers accepted out of 256 submissions) (36% acceptance rate)
Link*, G., N. Vijaykrishnan. March 2006. Thermal Trends in Emerging Technologies. Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006). pp. 625-632. San Jose, CA. (First author supervised by candidate) (93 regular papers accepted out of 256 submissions) (36% acceptance rate) (Nominated for Best Paper Award)
Hung, W.-L., G. Link*, Y. Xie, N. Vijaykrishnan, M. J. Irwin. March 2006. Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. Proceedings of the Seventh International Symposium on Quality Electronic Design (ISQED 2006). pp. 98-104. San Jose, CA. (Second author supervised by candidate) (93 regular papers accepted out of 256 submissions) (36% acceptance rate)
Wang, F., Y. Xie, N. Vijaykrishnan, M. J. Irwin. March 2006. On-chip Bus Thermal Analysis and Optimization. Proceedings of the Design, Automation and Test in Europe Conference (DATE 2006). pp. 850-855. Munich, Germany. (233 papers accepted out of 834 submissions) (28% acceptance rate)
Ricketts*, A. J., K. Irick*, N. Vijaykrishnan, M. J. Irwin. March 2006. Priority Scheduling in Digital Microfluidics-Based Biochips. Proceedings of the Design, Automation and Test in Europe Conference (DATE 2006). 329-334. Munich, Germany. (First two authors supervised by candidate) (233 papers accepted out of 834 submissions) (28% acceptance rate)
Kim, J., C. A. Nicopoulos*, D. Park, N. Vijaykrishnan, C. R. Das. March 2006. Performance Enhancement through Early Release and Buffer Optimization in Network-on-Chip Router Architectures. Special Workshop on Future Interconnects and Networks on Chip, in conjunction with the Design, Automation and Test in Europe (DATE 06). Proceedings on CD-ROM. Munich, Germany. (Poster) (Second author supervised by candidate)
Theocharides*, T., N. Vijaykrishnan, M. J. Irwin. March 2006. A Parallel Architecture for Hardware Face Detection. Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI 2006). pp. 452-454. Karlsruhe, Germany. (First author co-supervised by candidate) (Poster) (92 papers accepted out of 151 submissions)
Srinivasan*, S., N. Vijaykrishnan. March 2006. Variation Aware Placement Scheme for FPGAs. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006). pp. 422-424. Karlsruhe, Germany. (First author supervised by candidate) (Poster) (92 papers accepted out of 151 submissions)
Mutyam*, M., M. Eze, N. Vijaykrishnan, Y. Xie. March 2006. Delay and Energy Efficient Data Transmission for On-Chip Buses. Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI 2006). pp. 355-360. Karlsruhe, Germany. (First author supervised by candidate) (64 full papers accepted out of 151 submissions)
Yang*, S., W. Wolf, N. Vijaykrishnan, Y. Xie. March 2006. Reliability-aware SOC Voltage Islands Partition and Floorplan. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006). pp. 341-347. Karlsruhe, Germany. (First author supervised by candidate) (64 full papers accepted out of 151 submissions)
Chen, G., G. Chen, M. Kandemir, N. Vijaykrishanan, M. J. Irwin. January 2006. Object Duplication for Improving Reliability. Proceedings of the Eleventh Asia and South Pacific Design Automation Conference (ASP-DAC 2006). 140-145. Yokohama City, Japan. (135 out of 432 papers were accepted)
Richardson*, T., C. Nicopolus*, N. Vijaykrishnan, D. Park, Y. Xie C. R. Das. January 2006. A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. Proceedings of IEEE International Conference on VLSI Design. 657-664. Bangalore, India. (First author co-supervised and second author supervised) (88 regular papers accepted out of 328 submissions) (27% acceptance rate)
Ramanarayanan*, R., J. S. Kim*, N. Vijaykrishnan, Y. Xie, M. J. Irwin. January 2006. SEAT-LA: A Soft Error Analysis tool for Combinational Logic. Proceedings of Nineteenth International Conference on VLSI Design. 499-502. Bangalore, India. (First author co-supervised and second author supervised) (88 regular papers accepted out of 328 submissions) (27% acceptance rate)
Kim, J., D. Park, C. Nicopoulus, N. Vijaykrishnan, C. R. Das. October 2005. Design and Analysis of an NoC Architecture from Performance, Reliability and Energy Perspective. Proceedings of the First Symposium on Architectures for Networking and Communication Systems (ANCS 2005). pp. 173-182. Princeton, NJ. (Third author supervised by candidate) (23 accepted out of 100 submissions) (23% acceptance rate)
Pirretti, M. , N. Vijaykrishnan, M. Kandemir, R. Brooks. October 2005. Realistic Models for Sensor Networks Using Key Predistribution Schemes. Proceedings of the Innovations and Commercial Applications of Distributed Sensor Networks Symposium (ICA DSN). Proceedings on CD-ROM. Bethedsa, MD. (First author supervised)
Pirretti, M., S. Zhu, N. Vijaykrishnan, P. McDaniel, M. Kandemir, R. Brooks. October 2005. The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense. Proceedings of the Innovations and Commercial Applications of Distributed Sensor Networks Symposium (ICA DSN). Proceedings on CD-ROM. Bethedsa, MD. (First author supervised) (Selected as best paper)
Hung, W., G. Link, Y. Xie, N. Vijaykrishnan, N. Dhanwada J. Conner. October 2005. Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. Proceedings of the IEEE International Conference on Computer Design (ICCD 2005). 689-696. San Jose, CA. (Second author supervised by candidate) (101 papers accepted out of 313 submissions) (32% acceptance rate)
Tsai, Y., Y. Xie, N. Vijaykrishnan, M. J. Irwin. October 2005. Three-dimensional cache design using 3DCacti. Proceedings of the IEEE International Conference on Computer Design (ICCD 2005). 519-524. San Jose, CA. (First author supervised by candidate) (101 papers accepted out of 313 submissions) (32% acceptance rate)
Dhanwada, N., I. Lin, N. Vijaykrishnan. September 2005. A Power Estimation Methodology for SystemC Transaction Level Models. Proceedings of the International Conference on Hardware/Software Codesign and Synthesis (CODES + ISSS 2005). 142-147. New York, NY. (Second author co-supervised by candidate) (50 papers accepted out of 200 submissions)(25% acceptance rate)
Srinivasan, S., F. Angiolini, M. Ruggiero, N. Vijaykrishnan, L. Benini. September 2005. Simultaneous Memory and Bus Partitioning for SoC Architectures. Proceedings of the IEEE International SoC Conference (SOCC 2005). 125-128. Washington, D.C. (First author supervised by candidate)
Swankowski, E., N. Vijaykrishnan. September 2005. Dynamic High-Performance Multi-Mode Architectures for AES Encryption. Proceedings of the Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD’05). (CD ROM Proceedings). Washington, D.C.
Veezhinathan, K., Sk. Noor Mahammad, V. Muralidaran, N. Vijaykrishnan and V. Chandrasekar. September 2005. Reduced Triple Modular Redundancy for Tolerating SEUs in SRAM-based FPGA. Proceedings of the Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD’05). (CD ROM Proceedings). Washington, D.C.
Gayasen, A., N. Vijaykrishnan, M. J. Irwin. June 2005. Exploring Technology Alternatives for Nano-Scale FPGA Interconnects. Proceedings of the Forty-Second Design Automation Conference (DAC’05). pp. 921-926. Anaheim, CA. (First author co-supervised by candidate) (154 papers accepted out of 735 submissions) (21% acceptance rate)
Kim, J-H., D. Park, T. Theocharides, N. Vijaykrishnan, C. R. Das. June 2005. A Low Latency Router Supporting Adaptivity for On-Chip Interconnects. Proceedings of the Forty-Second Design Automation Conference (DAC’05). pp. 559-564. Anaheim, CA. (Third author supervised by candidate) (154 papers accepted out of 735 submissions) (21% acceptance rate)
Saputra, H., O. Ozturk, N. Vijaykrishnan, M. Kandemir, R. Brooks. May 2005. A Data-driven Approach for Embedded Security. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI ’05). 104-109. Tampa, FL. (First author co-supervised by candidate)
Lee, J., N. Vijaykrishnan, M. J. Irwin. May 2005. High Performance Array Processor for Video Decoding. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI ’05). 28-33. Tampa, FL. (First author co-supervised by candidate)
Reddy, S. S., E., V. Chandrasekhar, M. Sashikanth, V. Kamakoti Veezhinathan, N. Vijaykrishnan. April 2005. Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-based FPGAs. Proceedings of the Twelfth Reconfigurable Architectures Workshop (RAW 2005). 172a. Denver, CO.
Hung, W-L., Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, M. J. Irwin. March 2005. Thermal-Aware Floorplanning Using Genetic Algorithms. Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED 2005). pp. 634-639. San Jose, CA. (Fourth author supervised and fifth author co-supervised by candidate)
Hu, J., F. Li, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. March 2005. Compiler-directed Instruction Duplication for Soft Error Detection. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). 1056-1057. Munich, Germany. (Poster) (First and third authors supervised by candidate)
Hung, W-L., Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. March 2005. Thermal-Aware Allocation and Scheduling for Systems-on-a-Chip Design. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). 898-899. Munich, Germany (Poster)
Link, G., N. Vijaykrishnan. March 2005. Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip Designs. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). 648-649. Munich, Germany. (Poster) (First author supervised)
Tsai, Y-F., N. Vijaykrishnan, Y. Xie, M. J. Irwin. March 2005. Leakage-Aware Interconnect for On-Chip Network. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). 230-231. Munich, Germany. (Poster) (First author co-supervised by candidate)
Srinivasan, S., N. Vijaykrishnan. March 2005. Simultaneous Partitioning and Frequency Assignment for On-chip Bus Architectures. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). 218-223. Munich, Germany. (First author supervised by candidate) (176 papers accepted out of 825 submissions) (21% acceptance rate)
Yang, S., W. Wolf, N. Vijaykrishnan, Y. Xie. March 2005. Power Attack Resistant Crypto Design: A Dynamic Voltage and Frequency Switching Approach. Proceedings of the Design, Automation, and Test in Europe (DATE 2005). 64-69. Munich, Germany. (176 papers accepted out of 825 submissions) (21% acceptance rate)
Reddy, S. S., E., V. Chandrasekhar, M. Sashikanth, V. Kamakoti, N. Vijaykrishnan. January 2005. Cluster-based Detection of SEU-caused Errors in LUTs of SRAM-based FPGAs. Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC 2005). 1200-1203. Shanghai, China.
Srinivasan, S., A. Gayasen, N. Vijaykrishnan, T. Tuan. January 2005. Leakage Control in FPGA Routing Fabric. Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC 2005). 661-664. Shanghai, China. (First author supervised and second author co-supervised by candidate)
Yang, S., W. Wolf, W. Wang, N. Vijaykrishnan, Y. Xie. January 2005. Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies. Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC 2005). 539-544. Shanghai, China.
Reddy, S. S., E., S., M. Sashikanth, V. Chandrasekhar, N. Vijaykrishnan, V. Kamakoti. January 2005. Detecting SEU-caused Routing Errors in SRAM-based FPGAs. Proceedings of the Eighteenth International Conference on VLSI Design. 736-741. Kolkata, India. (97 regular papers accepted out of 352 submissions) (28% acceptance rate)
Tsai, Y-F., N. Vijaykrishnan, M. J. Irwin, Y. Xie. January 2005. Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. Proceedings of the Eighteenth International Conference on VLSI Design. 374-379. Kolkata, India. (First author co-supervised by candidate) (97 regular papers accepted out of 352 submissions) (28% acceptance rate)
Irick, K., W. Xu, N. Vijaykrishnan, M. J. Irwin. January 2005. A Nanosensor Array Based VLSI Gas Discriminator. Proceedings of the Eighteenth International Conference on VLSI Design. 241-248. Kolkata, India. (First author co-supervised and second author supervised by candidate) (97 regular papers accepted out of 352 submissions) (28% acceptance rate)
Yang, S., W. Wolf, W. Wang, N. Vijaykrishnan, Y. Xie. January 2005. Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. Proceedings of the Eighteenth International Conference on VLSI Design. 165-170. Kolkata, India. (97 regular papers accepted out of 352 submissions) (28% acceptance rate)
Theocharides, T., G. Link, N. Vijaykrishnan, M. J. Irwin. January 2005. Implementing LDPC Decoding on Network on Chip. Proceedings of the Eighteenth International Conference on VLSI Design. 134-137. Kolkata, India. (First author co-supervised and second author supervised by candidate)
Reddy, S. S., E., S. Kanth, V. Chandrasekhar, S. Srinivasan, N. Vijaykrishnan, V. Kamakoti. December 2004. A Novel CLB Architecture to Detect and Correct SEU in LUTs of SRAM-based FPGAs. Proceedings of the 2004 IEEE International Conference on Field- Programmable Technology (FPT’04). 121-128. Brisbane, Australia. (Accepted 34 full papers out of 122 submissions)
Kim, J. S., C. Nicopoulos, N. Vijaykrishnan, Y. Xie, E. Lattanzi. November 2004. A Probabilistic Model for Soft-Error Rate Estimation in Combinatorial Logic. Proceedings of the First International Workshop on Probabilistic Analysis Techniques for Real Time and Embedded Systems (PARTES 2004). Pisa, Italy.
Unlu, K., V. Degalahal, M. S. Cetiner, N. Vijaykrishnan, M. J. Irwin. November 2004. Testing Neutron-Included Soft Errors in Semiconductors. Proceedings of the American Nuclear Society Winter Meeting. 825-826. Washington, D.C. (Second author supervised by candidate) (Equal contributions by authors)
Srinivasan, S., A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. Xie, M. J. Irwin. November 2004. Improving Soft-error Tolerance of FPGA Configuration Bits. Proceedings of the International Conference on Computer Aided Design (ICCAD-2004). 107-110. San Jose, CA. (First author supervised and second author co-supervised by candidate) (24% acceptance rate)
Kang, B. T., N. Vijaykrishnan, M. J. Irwin. November 2004. Analyzing Software Influences on Substrate Noise: An ADC Perspective. Proceedings of the International Conference on Computer Aided Design (ICCAD-2004). 916-922. San Jose, CA. (Equal contributions by authors) (24% acceptance rate)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. October 2004. Field-level Analysis for Heap Space Optimization in Embedded Java. Proceedings of the International Symposium on Memory Management (ISMM’04). 131-142. Vancouver, British Columbia, Canada. (Contributing author) (35% acceptance rate)
Lee, J., N. Vijaykrishnan, M. J. Irwin, R. Radhakrishnan. October 2004. Inverse Discrete Cosine Transform Architecture Exploiting Sparseness and Symmetry Properties. Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS’04). 361-366. Austin, TX. (First author co-supervised by candidate)
Hung, W., C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijaykrishnan, M. J. Irwin. October 2004. Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. Proceedings of the International Conference on Computer Design (ICCD 2004). 430-437. San Jose, CA. (Second author supervised and fourth author co-supervised by candidate)
Xie, Y., L. Li, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. September 2004. Reliability-aware Cosynthesis for Embedded Systems. Proceedings of the Fifteenth IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP’04). 41-50. Galveston, TX. (Second author co-supervised by candidate)
Tsai, Y-F., A. Hegde, N. Vijaykrishnan, M. J. Irwin. September 2004. ChipPower: An Architecture-Level Leakage Simulator. Proceedings of the IEEE International Systems-on-Chip Conference (SOCC 2004). 395-398. Santa Clara, CA. (First author co-supervised by candidate)
Theocharides, T., G. Link, N. Vijaykrishnan, M. J. Irwin, V. Srikantam. September 2004. A Generic Reconfigurable Neural Network Architecture Implemented as a Network on Chip. Proceedings of the IEEE International Systems-on-Chip Conference (SOCC 2004). 191-194. Santa Clara, CA. (First author co-supervised and second author supervised by candidate)
Kang, B. T., N. Vijaykrishnan, M. J. Irwin, T. Theocharides. September 2004. Power-Efficient Implementation of Turbo Decoder in SDR Systems. Proceedings of the IEEE International Systems-on-Chip Conference (SOCC 2004). 119-122. Santa Clara, CA. (Fourth author supervised by candidate)
Chen, G., M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin. September 2004. Analyzing Object Error Behavior in Embedded JVM Environments. Proceedings of the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS’04). 230-235. Stockholm, Sweden. (Equal contributions by authors) (39 papers accepted out of 159 submissions) (25% acceptance rate)
Gayasen, A., K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, T. Tuan. August-September 2004. A Dual Vdd Low-power FPGA Architecture. Proceedings of the International Conference on Field-programmable Logic and Its Applications (FPL’04). 145-157. Antwerpen, Belgium. (First two authors co-chaired by candidate)
Hung, W., Y. Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. August 2004. Total Power Optimization Through Simultaneously Multiple-VDD Multiple-VTH Assignment and Device Sizing With Stack Forcing. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2004). 144-149. Newport Beach, CA. (Contributing author) (34% acceptance rate)
Li, L., V. Degalahal, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. August 2004. Soft Error and Energy Consumption Interactions: A Data Cache Perspective. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED 2004). 132-137. Newport Beach, CA. (First author co-supervised and second author supervised by candidate) (34% acceptance rate)
Yang, S., W. Wolf, N. Vijaykrishnan. June 2004. Search Speed and Power Driven Integrated Software and Hardware Optimizations for Motion Estimation Algorithms. Proceedings of the 2004 IEEE International Conference on Multimedia and Expo (ICME 2004). 707-710. Taipei, Taiwan. (Contributing author) [218 accepted out of 740 submissions] (29% acceptance rate)
Saputra, H., G. Chen, R. Brooks, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. June 2004. Code Protection for Resource-constrained Embedded Devices. Proceedings of the ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES ’04). 240-248. Washington, D.C. (First author supervised by candidate) [28 accepted out of 120 submissions] (23% acceptance rate)
Tsai, Y-F., D. Duarte, N. Vijaykrishnan, M. J. Irwin. May 2004. Impact of Process Scaling on the Efficacy of Leakage Reduction Scheme. Proceedings of the International Conference on IC Design and Technology (ICICDT 2004). 3-11. Austin, TX. (First author co-supervised by candidate)
Lee, J., N. Vijaykrishnan, M. J. Irwin. May 2004. Efficient VLSI Implementation of Inverse Discrete Cosine Transform. Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2004). 177-180. Montreal, Canada. (First author co-supervised by candidate) [1262 accepted out of 2,434 papers] (52% acceptance rate)
Xu, W., N. Vijaykrishnan, Y. Xie, M. J. Irwin. April 2004. Design of a Nanosensor Array Architecture. Proceedings of the 2004 Great Lakes Symposium on VLSI (GLSVLSI 2004). 298-303. Boston, MA. (First author supervised by candidate) [23 full papers accepted out of 235 submissions] (10% acceptance rate)
Lattanzi, E., A. Bogliolo, A. Gayasen, M. Kandemir, N. Vijaykrishnan, L. Benini. April 2004. Improving Java Performance by Dynamic Method Migration on FPGAs. Proceedings of the Eleventh Reconfigurable Architectures Workshop (RAW 2004). 134. Santa Fe, NM. (Third author co-supervised by candidate)
Swankoski, E., R. Brooks, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. April 2004. A Parallel Architecture for Secure FPGA Symmetric Encryption. Proceedings of the Eleventh Reconfigurable Architectures Workshop (RAW 2004). 132. Santa Fe, NM.
Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, M. J. Irwin. March 2004. The Effect of Threshold Voltages on the Soft Error Rate. Proceedings of the Fifth International Symposium on Quality Electronic Design (ISQED 2004). 503-508. San Jose, CA. (First author supervised and second author co-supervised by candidate)
Gayasen, A., Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2004. Reducing Leakage Energy in FPGAs Using Region-constrained Placement. Proceedings of the ACM International Symposium on Field-Programmable Gate Arrays (FPGA’04). 51-58. Monterey, CA. (First author co-supervised by candidate)
Theocharides, T., G. Link, E. Swankoski, N. Vijaykrishnan, M. J. Irwin, H.Schmit. February 2004. Evaluating Alternative Implementations for LDPC Decoder Check Node Function. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004). 77-82. Lafayette, LA. (First author co-supervised and second author supervised by candidate) [29 accepted out of 123 submissions] (24% acceptance rate)
Pirreti, M., G. Link, R. Brooks, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2004. Fault-tolerant Algorithms for Network-on-chip Interconnect. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004). 46-51. Lafayette, LA. (Second author supervised by candidate) [29 accepted out of 123 submissions] (24% acceptance rate)
Kadayif, I., I. Kolcu, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. February 2004. Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessor. Proceedings of the Design Automation and Test in Europe Conference (DATE’04). Volume 2, pp. 158-163. Paris, France. [181 accepted out of 780 submissions] (23% acceptance rate)
Hu, J. S., N. Vijaykrishnan, S. Kim, M. Kandemir, M. J. Irwin. February 2004. Scheduling Reusable Instructions for Power Reduction. Proceedings of the Design Automation and Test in Europe Conference (DATE’04). Volume 1, pp. 148-155. Paris, France. (First author supervised by candidate) [181 accepted out of 780 submissions] (23% acceptance rate)
Li, L., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. February 2004. A Crosstalk Aware Interconnect with Variable Cycle Transmission. Proceedings of the Design Automation and Test in Europe Conference (DATE’04). Volume 1, pp. 102-107. Paris, France. (First author co-supervised by candidate) [181 accepted out of 780 submissions] (23% acceptance rate)
Hu, J. S., N. Vijaykrishnan, M. J. Irwin. February 2004. Exploring Wakeup-Free Instruction Scheduling. Proceedings of the Tenth International Symposium on High Performance Computer Architecture (HPCA-10). 232-243. Madrid, Spain. (First author supervised by candidate) [27 accepted out of 151 submissions] (17.8% acceptance rate)
Lee, J., N. Vijaykrishnan, M. J. Irwin, W. Wolf. January 2004. An Architecture for Motion Estimation in the Transform Domain. Proceedings of the Seventeenth International Conference on VLSI Design. 1077-1082. Mumbai, India. (First author co-supervised by candidate)
Derenzo, M., M. J. Irwin, N. Vijaykrishnan. January 2004. Designing Leakage-Aware Multipliers. Proceedings of the Seventeenth International Conference on VLSI Design. 654-657. Mumbai, India.
Theocharides, T., G. Link, N. Vijaykrishnan, M. J. Irwin, W. Wolf. January 2004. Embedded Hardware Face Detection. Proceedings of the Seventeenth International Conference on VLSI Design. 133-138. Mumbai, India. (First author co-supervised and second author supervised by candidate)
Yang, S., W. Wolf, N. Vijaykrishnan. December 2003. Power Modeling of VLSI Motion Estimation Architecture. Proceedings of the Fifth Workshop on Media and Streaming Processors (MSP), held in conjunction with MICRO-6. 39-49. San Diego, CA.
Vijaykrishnan, N. December 2003. Designing Energy-Efficient and Reliable Hardware. Proceedings of the IFIP International Conference on VLSI. 6-9. Darmstadt, Germany (Invited)
Li, L., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. November 2003. Adaptive Error Protection for Energy Efficiency. Proceedings of the International Conference on Computer Aided Design (ICCAD-2003). 2-7. San Jose, CA. [130 accepted out of 490 submissions] (26.5% acceptance rate) (First author co-supervised by candidate)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, B. Mathiske, M. Wolczko. October 2003. Heap Compression for Memory-constrained Java Environments. Proceedings of the Eighteenth Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA’03). 282-301. Anaheim, CA. [26 accepted out of 142 submissions] (18.3% acceptance rate)
De La Luz, V., A. Sivasubramaniam, M. Kandemir, M. J. Irwin, N. Vijaykrishnan. October 2003. Reducing dTLB Energy Through Dynamic Resizing. Proceedings of the Twenty-First International Conference on Computer Design (ICCD). 358-363. San Jose, CA. [78 accepted out of 233 submissions] (33.4% acceptance rate)
Chen, G., N. Vijaykrishnan, M. Kandemir, M. J. Irwin, M. Wolczko. October 2003. Tracking Object Life Cycle for Leakage Energy Optimization. Proceedings of the CODES-ISSS Merged Conference (CODES/ISSS’03). 213-218. Newport Beach, CA. [30 accepted out of 143 submissions] (21% acceptance rate)
Hegde, A., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. October 2003. VL-CDRAM: Variable Line Sized Cached DRAMs. Proceedings of the CODES-ISSS Merged Conference (CODES/ISSS’03). 132-137. Newport Beach, CA. (First author supervised by candidate) [30 accepted out of 143 submissions] (21% acceptance rate)
Duarte, D., N. Vijaykrishnan, M. J. Irwin. September 2003. Energy and Timing Characterization of VLSI Charge-pump Phase-locked Loops. Proceedings of the IEEE International SOC Conference (ASIC/SOC’03). 341-344. Portland, OR.
Kang, B., N. Vijaykrishnan, M. J. Irwin, D. Duarte. September 2003. Substrate Noise Detector for Noise Tolerant Mixed-Signal IC. Proceedings of the IEEE International SOC Conference (ASIC/SOC’03). 279-280. Portland, OR. (First author co-supervised by candidate)
Ramanarayanan, R., V. Degalahal, N. Vijaykrishnan, M. J. Irwin, D. Duarte. September 2003. Analysis of Soft-Error Rate for Flip-Flops and Scannable Latches. Proceedings of the IEEE International SOC Conference (ASIC/SOC’03). 231-234. Portland, OR. (First author co-supervised and second author supervised by candidate)
Chen, G., G. Chen, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. September 2003. Energy-aware Code Cache Management for Memory-constrained Java Devices. Proceedings of the IEEE International SOC Conference (ASIC/SOC’03). 179-182. Portland, OR.
Li, L., N. Vijaykrishnan, M. Kandemir, M. J. Irwin, I. Kadayif. September 2003. CCC: Crossbar Connected Caches for Reducing Energy. Proceedings of the Euromicro Symposium on Digital System Design (DSD’2003). 41-48. Belek, Turkey.
Lee, J., N. Vijaykrishnan, M. J. Irwin, R. Chandramouli. August 2003. An Efficient Implementation of Hierarchical Image Coding. Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS’03). 363-368. Seoul, Korea. (First author co-supervised by candidate)
Saputra, H., N. Vijaykrishnan, M. Kandemir, R. Brooks, M. J. Irwin. August 2003. Exploiting Value Locality for Secure Energy Aware Communication. Proceedings of the IEEE Workshop on Signal Processing Systems (SIPS’03). 116-121. Seoul, Korea. (First author co-supervised by candidate)
Kim, E. J., K. H. Yum, G. Link, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, C. R. Das. August 2003. Energy Optimization Techniques in Cluster Interconnects. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’03). 459-464. Seoul, Korea. (Third author supervised by candidate) [17 accepted as long out of 221 submissions] (7.6% acceptance rate)
Hu, J. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. August 2003. Exploiting Program Hotspots and Code Sequentiality for Instruction Cache Leakage Management. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’03). 402-407. Seoul, Korea. (First author supervised by candidate) [91 accepted out of 221 submissions] (41% acceptance rate)
Kim, S., N. Vijaykrishnan, M. J. Irwin, L. K. John. August 2003. On Load Latency in Low-Power Caches. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’03). 258-261. Seoul, Korea. (First author supervised by candidate) [91 accepted out of 221 submissions] (41% acceptance rate)
Kim, H. S., N. Vijaykrishnan, M. Kandemir, E. Brockmeyer, F. Catthoor, M. J. Irwin. August 2003. Estimating Influence of Data Layout Optimizations on SDRAM Energy Consumption. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED’03). 40-43. Seoul, Korea. (First author supervised by candidate) [91 accepted out of 221 submissions] (41% acceptance rate)
Bhatkar, A., R. Chandramouli, N. Vijaykrishnan, M. J. Irwin. July 2003. Computation and Transmission Energy Modeling Through Profiling for MPEG4 Video Transmission. Proceedings of the IEEE International Conference on Multimedia & Expo (ICME 2003). Volume 1, pp. 281-284. Baltimore, MD.
Kim, H. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. June 2003. Adapting Instruction Level Parallelism for Optimizing Leakage in VLIW Architectures. Proceedings of the Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES’03). 275-283. San Diego, CA. [29 accepted out of 128 submissions] (23% acceptance rate)
Tsai, Y-F., D. Duarte, N. Vijaykrishnan, M. J. Irwin. June 2003. Implications of Technology Scaling on Leakage Reduction Techniques. Proceedings of the Fortieth Design Automation Conference. 187-190. Anaheim, CA. (First author co-supervised by candidate) (24% acceptance rate)
Schmit, H., T. Kroll, M. Khusid, I. Kourtev, N. Vijaykrishnan, D. Landis. June 2003. The Sandbox Experience Course. Proceedings of the International Conference on Microsystem Education. 41-42. Anaheim, CA.
Chen, G., B. Kang, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, R. Chandramouli. April 2003. Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS 2003). (CD-ROM). Nice, France. (Second author co-supervised by candidate) [119 accepted out of 407 submissions] (29.3% acceptance rate)
Gurumurthi, S., N. An, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. April 2003. Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS 2003). (CD-ROM). Nice, France. [119 accepted out of 407 submissions] (29.3% acceptance rate)
Zhang, W., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, V. De. March 2003. Compiler Support for Reducing Leakage Energy Consumption. Proceedings of International Conference on Design Automation and Test in Europe (DATE 2003). 11146-11147. Munich, Germany. (Equal contributions by authors) [20 accepted out of 590 submissions] (34% acceptance rate)
Saputra, H., N. Vijaykrishnan, M. Kandemir, M. J. Irwin, R. Brooks, S. Kim, W. Zhang. March 2003. Masking the Energy Behavior of DES Encryption. Proceedings of International Conference on Design Automation and Test in Europe (DATE 2003). 10084-10089. Munich, Germany. (First author co-supervised by candidate) (Equal contributions) [98 long papers accepted out of 590 submissions] (16.6% acceptance rate for long papers)
Gurumurthi, S., J. Zhang, A. Sivasubramaniam, M. Kandemir, H. Franke, N. Vijaykrishnan, M. J. Irwin. March 2003. Interplay of Energy and Performance for Disk Arrays Running Transaction Processing Workloads. Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS’03). 123-132. Austin, TX. (Contributing author) [22 accepted out pf 62 submissions] (35.4% acceptance rate)
Hu, J. S., N. Vijaykrishnan, M. J. Irwin, M. Kandemir. February 2003. Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. Proceedings of the IEEE Annual Symposium on VLSI (ISVLSI’03). 127-132. Tampa, FL. (First author supervised by candidate) [26 accepted out of 115 submissions] (22.6% acceptance rate)
Degalahal, V., N. Vijaykrishnan, M. J. Irwin. January 2003. Analyzing Soft Errors in Leakage Optimized SRAM Designs. Proceedings of the Sixteenth International Conference on VLSI Design. 539-545. New Delhi, India. (First author supervised by candidate) [84 accepted out of 210 submissions] (40% acceptance rate)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. November 2002. PennBench: A Benchmark Suite for Embedded Java. Proceedings of the Fifth Annual IEEE Workshop on Workload Characterization (WWC’02). 71-80. Austin, TX. (Equal contributions by authors)
Zhang, W., J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, and M. J. Irwin. November 2002. Compiler-directed instruction cache leakage optimization. Proceedings of the Thirty-Fifth Annual International Symposium on Microarchitecture (MICRO-35). pp. 208-218. Istanbul, Turkey. (Second and third authors supervised by candidate) (Equal contributions by authors) (36 accepted out of 150 submissions) (24% acceptance rate)
Li, T., L. K. John, A. Sivasubramaniam, N. Vijaykrishnan, J. Rubio. October 2002. Understanding and Improving Operating System Effects in Control Flow Transfer. Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X). San Jose, CA. 68-80. (Contributing author) [24 accepted out of 130 submissions] (18% acceptance rate)
Charles, D., A. Hurson, N. Vijaykrishnan. October 2002. Improving ILP with Instruction-reuse Cache Hierarchy. Proceedings of the Fifth International Conference on Algorithms and Architectures for Parallel Processing. 206-213. Beijing, China. (First author supervised by candidate)
Zhao, J., R. Chandramouli, N. Vijaykrishnan, M. J. Irwin, B. Kang, S. Somasundaram. September 2002. Influence of MPEG-4 Parameters on System Energy. Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference. 137-142. Rochester, NY. (First author supervised and fifth author co-supervised by candidate)
Esakkimuthu, G., N. Vijaykrishnan, M. J. Irwin. September 2002. An Analytical Power Estimation Model for Crossbar Interconnects. Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference. pp.119-123. Rochester, NY. (First author supervised by candidate)
Ramanarayanan, R., N. Vijaykrishnan, M. J. Irwin. September 2002. Characterizing Dynamic and Leakage Power Behavior in Flip-Flops. Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference. 433-437. Rochester, NY. (First author co-supervised by candidate)
Duarte, D., N. Vijaykrishnan, M. J. Irwin. September 2002. Impact of Technology Scaling and Packaging on Dynamic Voltage Scaling Techniques. Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference. 244-248. Rochester, NY. (Contributing author)
Kim, S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. September 2002. Predictive Precharging for Bitline Leakage Energy Reduction. Proceedings of the Fifteenth Annual IEEE International ASIC/SOC Conference. pp. 36-40. Rochester, NY. (First author supervised by candidate)
Li, L., I. Kadayif, Y-F. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, A. Sivasubramaniam. September 2002. Leakage Energy Management in Cache Hierarchies. Proceedings of the Eleventh International Conference on Parallel Architectures and Compilation Techniques (PACT 2002). 131-140. Charlottesville, VA. (First and third authors co-supervised by candidate) [25 accepted out of 119 submissions] (21% acceptance rate)
Duarte, D., N. Vijaykrishnan, M. J. Irwin, H. S. Kim, G. McFarland. September 2002. Scaling of the Effectiveness of Power Reduction Schemes and the Impact of Temperature Management. Proceedings of the International Conference on Computer Design (ICCD 2002). 382-387 Freiburg, Germany. (Fourth author supervised by candidate) [47 long papers accepted out of 173 submissions] (27% acceptance rate)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, M. Wolczko. August 2002. Adaptive Garbage Collection for Battery-Operated Environments. Proceedings of the Second USENIX JavaTM Virtual Machine Research and Technology Symposium (JVM’02). pp. 1-12. San Francisco, CA. (Equal Contributions by authors) [18 accepted out of 50 submissions] (36% acceptance rate)
De La Luz, V., A. Sivasubramaniam, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. June 2002. Scheduler-Based DRAM Energy Management. Proceedings of the Thirty-Ninth Design Automation Conference (DAC). 697-702. New Orleans, LA. (Contributing author) [148 accepted out of 491 submissions] (30% acceptance rate)
Hu, J. S., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, H. Saputra, W. Zhang. June 2002. Compiler-Directed Cache Polymorphism. Proceedings of the ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES’02) and Software and Compilers for Embedded Systems (SCOPES’02). 165-174. Berlin, Germany. (First author supervised and fifth author co-supervised by candidate) [25 accepted out of 73 submissions] (34% acceptance rate)
Saputra, H., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. S. Hu, C-H. Hsu, U. Kremer. June 2002. Energy-Conscious Compilation Based on Voltage Scaling. Proceedings of the ACM SIGPLAN Joint Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES’02) and Software and Compilers for Embedded Systems (SCOPES’02). 2-10. Berlin, Germany. (First author co-supervised and fifth author supervised by candidate) [25 accepted out of 73 submissions] (34% acceptance rate)
Chen, G., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, W. Wolf. May 2002. Energy Savings Through Compression in Embedded Java Environments. Proceedings of the ACM/SIGDA/SIGSOFT Tenth International Conference on Hardware/Software Codesign (CODES ’02). 163-168. Estes Park, CO. (Equal contributions by authors) [25 full papers accepted out of 75 submissions] (33% acceptance rate)
Kang, B-T., N. Vijaykrishnan, M. J. Irwin, R. Chandramouli. May 2002. Power Efficient Adaptive M-QAM Design Using Adaptive Pipelined Analog-to-Digital Converter. Proceedings of the International Conference on Acoustics, Speech and Signal Processing (ICASSP 2002). (CD ROM Proceedings). Orlando, FL. (First author co-supervised by candidate) [1007 accepted out of 1770 submissions] (56% acceptance rate)
Kadayif, I., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. April 2002. Hardware-Software Co-Adaption for Data-Intensive Embedded Applications. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002). 20-25. Pittsburgh, PA. (Equal contributions by authors)
Duarte, D., N. Vijaykrishnan, M. J. Irwin, Y-F. Tsai. April 2002. Impact of Technology Scaling on the Clock System Power. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002). 59-64. Pittsburgh, PA. (Fourth author co-supervised by candidate)
Sivasubramaniam, A., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. April 2002. Designing Energy-Efficient Software. Proceedings of the Next Generation Software Workshop, held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS 2002). 176. Fort Lauderdale, FL. (Equal contributions by authors)
Kadayif, I., N. Orr, M. Kandemir, N. Vijaykrishnan, M. J. Irwin. March 2002. Instruction Selection/Scheduling Using an Energy-aware Instruction Set Architecture. Proceedings of the Sixth Workshop of Languages, Compilers, and Runtime Systems for Scalable Computers (LCR ’02). 1-10. Washington, D.C.
Duarte, D., N. Vijaykrishnan, M. J. Irwin. March 2002. A Complete Phase-Locked Loop Power Consumption Model. Proceedings of International Conference on Design Automation and Test in Europe (DATE 2002). 1108. Paris, France. (Contributing author) (44% acceptance rate)
Hu, J. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. March 2002. Power-Efficient Trace Caches. Proceedings of International Conference on Design Automation and Test in Europe (DATE 2002). p. 1091. Paris, France. (First author supervised by candidate) (44% acceptance rate)
Kadayif, I., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam. March 2002. EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. Proceedings of the International Conference on Design Automation and Test in Europe (DATE). 436-442. Paris, France. (Equal contributions by authors) [88 accepted as long papers out of 476 submissions] (18% acceptance rate for long papers)
Gurumurthi, S., A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan, M. Kandemir, T. Li, L. K. John. February 2002. Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA-8). 141-150. Cambridge, MA. (Equal contributions by Authors) [26 accepted out of 130 submissions] (20% acceptance rate)
Chen, G., R. Shetty, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, M. Wolczko. February 2002. Tuning Garbage Collection in an Embedded Java Environment. Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA-8). 92-103. Cambridge, MA. (Second author supervised) [26 accepted out of 130 submissions] (20% acceptance rate)
Duarte, D., Y-F. Tsai, N. Vijaykrishnan, M. J. Irwin. January 2002. Evaluating Run-Time Techniques for Leakage Power Reduction. Proceedings of the Seventh Asia and South Pacific Design Automation Conference and the Fifteenth International Conference on VLSI Design (VLSI Design/ASP-DAC ’02). Bangalore, India. 31-38. (Second author co-supervised) [113 accepted out of 269 submissions] (42% acceptance rate)
De La Luz, V., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam, I. Kolcu. January 2002. Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. Proceedings of the Seventh Asia and South Pacific Design Automation Conference (ASP-DAC ’02) and the Fifteenth International Conference on VLSI Design (VLSI Design 2002). 288-293. Bangalore, India. (Contributing author) [113 accepted out of 269 submissions] (42% acceptance rate)
Zhang, W., N. Vijaykrishnan, M. Kandemir, M. J. Irwin, D. Duarte, Y-F. Tsai. December 2001. Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction. Proceedings of the Thirty-Fourth Annual International Symposium on Microarchitecture (MICRO-34). 102-113. Austin, TX. (Equal contributions by authors) (Sixth author co-supervised by candidate) (Equal contributions by authors) [29 accepted out of 144 submissions] (20% acceptance rate)
Kirubanandan, N., A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. December 2001. Memory Energy Characterization and Optimization for the SPEC2000 Benchmarks. Proceedings of the IEEE Fourth Annual Workshop on Workload Characterization (WWC-4) (held in conjunction with MICRO-34). 193-201. Austin, TX. (First author supervised by candidate) (~50% acceptance rate)
Kim, S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. November 2001. Energy-Efficient Instruction Cache Using Page-Based Placement. Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2001). 229-237. Atlanta, GA. (First author supervised by candidate) [28 accepted out 80 submissions] (35% acceptance rate)
Duarte, D., N. Vijaykrishnan, M. J. Irwin, M. Kandemir. September 2001. Evaluating the Impact of Architectural-Level Optimizations on Clock Power. Proceedings of the Fourteenth Annual IEEE International ASIC/SOC Conference. 447-451. Washington, D.C. (Contributing author) (Proceedings were published, but Conference was cancelled due to National Disaster)
Thirugnanam, G., N. Vijaykrishnan, M. J. Irwin. September 2001. A Novel Low Power CAM Design. Proceedings of the Fourteenth Annual IEEE International ASIC/SOC Conference. 198-202. Washington, D.C. (First author supervised) (Proceedings were published, but Conference was cancelled due to National Disaster)
Tomar, S., S. Kim, N. Vijaykrishnan, M. Kandemir, M. J. Irwin. September 2001. Use of Local Memory for Efficient Java Execution. Proceedings of the International Conference on Computer Design (ICCD 2001). 468-473. Austin, TX. (First and second authors supervised by candidate) [61 accepted out of 181 submissions] (34% acceptance rate)
Kim, H. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. September 2001. A Framework for Exploring Energy-Efficient VLIW Architectures. Proceedings of the International Conference on Computer Design (ICCD 2001). 40-45. Austin, TX. (First author supervised) [61 accepted out of 181 submissions] (34% acceptance rate)
Hezavei, J., N. Vijaykrishnan, M. J. Irwin, M. Kandemir, D. Duarte. September 2001. Input Sensitive High-level Power Analysis. Proceedings of the 2001 IEEE Workshop on SiGNAL Processing Systems (SiPS 2001). 149-156. Antwerp, Belgium. (First author supervised by candidate) (~70% acceptance rate)
An, N., A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, S. Gurumurthi. September 2001. Analyzing Energy Behavior of Spatial Access Methods for Memory-Resident Data. Proceedings of the Twenty Seventh International Conference on Very Large Databases (VLDB 2001). 411-420. Rome, Italy. (Contributing author) [59 accepted out of 339 submissions] (17% acceptance rate)
Kim, S., N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, E. Geethanjali. August 2001. Power-aware Partitioned Cache Architectures. Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED ’01). 64-67. Huntingdon Beach, CA. (First and sixth authors supervised by candidate) [73 accepted out of 194 submissions] (38% acceptance rate)
Khosla, P., H. Schmit, M. J. Irwin, N. Vijaykrishnan, T. Cain, S. Levitan, D. Landis. June 2001. SoC Design Skills: Collaboration Builds a Stronger SoC Design Team. Proceedings of the 2001 International Conference on Microelectronic Systems Education (MSE 2001). 42-43. Las Vegas, NV. (Contributing author)
Kadayif, I., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, J. Ramanujam. June 2001. Morphable Cache Architectures: Potential Benefits. Proceedings of ACM Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001). 128-137. Snowbird, UT. (Equal contributions by authors) [20 accepted out of 68 submissions] (29% acceptance rate)
Kadayif, I., T. Chinoda, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, A. Sivasubramaniam. June 2001. vEC: Virtual Energy Counters. Proceedings of ACM SIGPLAN/SIGSOFT Workshop on Program Analysis for Software Tools and Engineering (PASTE ’01). 28-31. Snowbird, UT. (Second author supervised by candidate) (First two authors equal contribution)
Kandemir, M., J. Ramanujam, M. J. Irwin, N. Vijaykrishnan, I. Kadayif, A. Parikh. June 2001. Dynamic Management of Scratch-pad Memory Space. Proceedings of the Thirty-Eighth Design Automation Conference (DAC ’01). 690-695. Las Vegas, NV. (Contributing author) [160 accepted out of 410 submissions] (39% acceptance rate)
Athavale, R., Vijaykrishnan, M. Kandemir, M. J. Irwin. April 2001. Influence of Array Allocation Mechanisms on Memory System Energy. Proceedings of the Fifteenth International Parallel and Distributed Processing Symposium (IPDPS 2001). p. 3 (full paper on CD-ROM). San Francisco, CA. (First author supervised by candidate) (Equal contributions by authors) [48 long papers accepted out of 276 submissions] (17% acceptance rate for long papers)
Parikh, A., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. April 2001. VLIW Scheduling for Energy and Performance. Proceedings of IEEE Computer Society Annual Workshop on VLSI (WVLSI 2001). 111-117. Orlando, FL. (Equal contributions by authors)
Vijaykrishnan, N., M. Kandemir, S. Tomar, S. Kim, A. Sivasubramaniam, M. J. Irwin. April 2001. Energy Behavior of Java Applications from the Memory Perspective. Proceedings of the Java Virtual Machine Research & Technology Symposium (JVM ’01). 207-220. Monterey, CA. (Third/fourth author supervised by candidate) (Principal author) [18 accepted out of 50 submissions] (36% acceptance rate)
Tomar, S., N. Vijaykrishnan, M. Kandemir, R. Shetty. April 2001. Energy Optimization Using Object Co-Location in Java. JOSES: Java Optimization Strategies for Embedded Systems Workshop in conjunction with ETAPS 2001. 9-15. Genova, Italy. (First and fourth authors supervised) (Equal contributions by authors)
De La Luz, V., M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam, M. J. Irwin. January 2001. DRAM Energy Management Using Software and Hardware Directed Power Mode Control. Proceedings of the Seventh International Symposium on High Performance Computer Architecture (HPCA 2001). 159-169. Monterrey, Mexico. (Equal contributions by authors) [26 accepted out of 110 submissions] (23% acceptance rate)
Duarte, N. Vijaykrishnan, M. J. Irwin, M. Kandemir. January 2001. Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks. Proceedings of the Fourteenth International Conference on VLSI Design. 248-253. Bangalore, India. (Contributing author) (~35% acceptance rate)
Parikh, A., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. December 2000. Instruction Scheduling. Proceedings of the Seventh International Conference on High Performance Computing (HiPC 2000). Springer-Verlag Lecture Notes in Computer Science 1970:335-344. Bangalore, India. (Equal contributions by authors) [46 accepted out of 127 submissions] (36% acceptance rate)
Juran, J., A. R. Hurson, N. Vijaykrishnan, S. Boonsiriwattanakul. December 2000. Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues. Proceedings of the Seventh International Conference on High Performance Computing (HiPC 2000). Springer-Verlag Lecture Notes in Computer Science 1970:501-510. Bangalore, India. (Contributing author) [46 accepted out of 127 submissions] (36% acceptance rate)
De La Luz, V., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. November 2000. Energy-Oriented Compiler Optimizations for Partitioned Memory Architectures. Proceedings of the Third International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2000). 138-147. San Jose, CA. (Contributing author) [25 accepted out of 56 submissions] (44% acceptance rate)
Kim, H. S., M. J. Irwin, N. Vijaykrishnan, M. Kandemir. October 2000. Effect of Compiler Optimizations on Memory Energy. Proceedings of IEEE Workshop on Signal Processing Systems (SiPS ’00). 663-672. Lafayette, LA. (First author supervised) [83 accepted out of 115 submissions] (72% acceptance rate)
Irwin, M. J., M. Kandemir, N. Vijaykrishnan, A. Sivasubramaniam. September 2000. A Holistic Approach to System Level Energy Optimization. Proceedings of the Tenth International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2000). Edited by Soudris, P. Pirsch, E. Barke. Springer-Verlag LNCS 1918:88-107. Göttingen, Germany. (Equal contributions by authors) (Invited)
Lyuboslavsky, V., B. Bishop, N. Vijaykrishnan, M. J. Irwin. September 2000. Design of Databus Charge-Recovery Mechanism. Proceedings of the International Conference on ASIC. pp. 283-287. Washington, D.C. (First author supervised)
Duarte, D., M. J. Irwin, N. Vijaykrishnan. September 2000. Modeling Energy of the Clock Generation and Distribution Circuitry. Proceedings of the International Conference on ASIC. 261-265. Washington, D.C. (Contributing author)
Athavale, R., N. Vijaykrishnan, M. Kandemir. September 2000. Annotation Based Energy Optimization Using Array Interleaving. Proceedings of the Second Annual Workshop on Hardware Spport for Objects and Microarchitectures for Java. 16-20. Austin, TX. (First author supervised) (~70% acceptance rate)
Kandemir, M., N. Vijaykrishnan, M. J. Irwin, H. S. Kim. August 2000. Experimental Evaluation of Energy Behavior of Iteration Space Tiling. Proceedings of the Thirteenth Annual Workshop on Languages and Compilers for Parallel Computing (LCPC’00). Springer-Verlag Lecture Notes in Computer Science 2017:142-157. Yorktown Heights, NY. (Equal contributions by authors)
Esakkimuthu, G., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. July 2000. Memory System Energy: Influence of Hardware-Software Optimizations. Proceedings of ISLPED’2000. 244-246. Rapallo, Italy. (First author supervised) [57 accepted out of 162 submissions] (35% acceptance rate)
Kandemir, M., N. Vijaykrishnan, M. J. Irwin, H. S. Kim. June 2000. Towards Energy Aware Iteration Space Tiling. Proceedings of ACM Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2000). LNCS 1985, pp. 211-215. Vancouver, British Columbia, Canada. (Equal contributions by authors) [17 accepted out of 43 submissions] (40% acceptance rate)
Vijaykrishnan, N., M. Kandemir, M. J. Irwin, H. S. Kim, W. Ye. June 2000. Energy-Driven Integrated Hardware-Software Optimization Using SimplePower. Proceedings of the Twenty-Seventh Annual International Symposium on Computer Architecture (ISCA-2000). pp. 95-106. Vancouver, British Columbia, Canada. (Equal contributions by authors) [29 accepted out of 166 submissions] (17% acceptance rate)
Ye, W., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. June 2000. The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool. Proceedings of Thirty-Seventh Design Automation Conference (DAC’00). pp. 340-345. Los Angeles, CA. (Equal contributions by authors) [154 accepted out of 445 submissions] (34% acceptance rate)
Kandemir, M., N. Vijaykrishnan, M. J. Irwin, W. Ye. June 2000. Influences of Compiler Optimizations on System Power. Proceedings of Thirty-Seventh Design Automation Conference (DAC ’00). 304-307. Los Angeles, CA. (Equal contributions by authors) [154 accepted out of 445 submissions] (34% acceptance rate)
Tao, L., L. John, N. Vijaykrishnan, A. Sivasubramaniam, A. Murthy, J. Sabarinathan. May 2000. Using Complete System Simulation to Characterize SPECjvm98 Benchmarks. Proceedings of the International Conference on Supercomputing (ICS ’00). 22-33. Santa Fe, New Mexico. (Equal contributions by authors) [33 accepted out of 122 submissions] (28% acceptance rate)
Parikh, A., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. April 2000. Instruction Scheduling Based on Energy and Performance Constraints. Proceedings of the IEEE CS Annual Workshop on VLSI (WVLSI 2000). pp. 53-58. Orlando, FL. (Equal contributions by authors)
Kim, H. S., N. Vijaykrishnan, M. Kandemir, M. J. Irwin. April 2000. Multiple Access Caches: Energy Implications. Proceedings of the IEEE CS Annual Workshop on VLSI (WVLSI 2000). pp. 37-42. Orlando, FL. (First author supervised)
Hezavei, J., N. Vijaykrishnan, M. J. Irwin. March 2000. A Comparative Study of Power Efficient SRAM Design. Proceedings of the Tenth Great Lakes Symposium on VLSI (GLSVLSI-2000). pp. 117-122. Evanston, Illinois. (First author supervised)
Radhakrishnan, R., N. Vijaykrishnan, L. K. John, A. Sivasubramaniam. January 2000. Execution Characteristics of Java Run-time Systems. Proceedings of the International Symposium on High Performance Computer Architecture (HPCA-6). pp. 387-398. Toulouse, France. (First two authors equal contributions; third and fourth author contributing) [35 accepted out of 163 submissions] (21% acceptance rate)
Irwin, M. J., N. Vijaykrishnan. October 1999. Energy Issues in Multimedia Systems. Proceedings of the Workshop on Signal Processing Systems. pp. 24-33. Taipei, Taiwan. (Equal contributions by authors) (Invited)
Murthy, A., N. Vijaykrishnan and A. Sivasubramaniam. October 1999. How Can Hardware Support Just-in-Time Compilation? Proceedings of the Workshop on Hardware Support for Objects and Microarchitectures for Java. pp. 15-19. (Principal author) (~67% acceptance rate)
Boonsiriwattanakul, S., A. R. Hurson, N. Vijaykrishnan, C. Chehadeh. July-August 1999. Energy-Efficient Indexing on Parallel Air Channels in a Mobile Database Access System. Proceedings of the Third World Multiconference on Systemics, Cybernetics and Informatics (SCI ’99) and the Fifth International Conference on Information Systems Analysis and Synthesis (ISAS ’99). 4:30-38. Orlando, FL. (Contributing author) [759 accepted out of 950 submissions] (80% acceptance rate)
Vijaykrishnan, N., N. Ranganathan. May 1999. Tuning Branch Predictors to Support Java Method Invocation. Proceedings of the Fifth USENIX Conference on Object-Oriented Technologies and Systems (COOTS ’99). pp. 217-228. San Diego, CA. (Principal author) [17 accepted out of 61 submissions] (27% acceptance rate)
Chen, R. Y., N. Vijaykrishnan, M. J. Irwin. April 1999. Clock Power Issues in System-on-a-Chip Designs. Proceedings of the IEEE Computer Society Annual Workshop on VLSI: System Level Design (WVLSI ’99). pp. 48-53. Orlando, FL. (Equal contributions by authors)
Krishna, V., N. Ranganathan, N. Vijaykrishnan. January 1999. Efficient Energy Reduction Using Dynamic Frequency Clocking and Multiple Voltages. Proceedings of the Twelfth International Conference on VLSI Design. pp. 440-445. Goa, India. (Equal contributions by authors) (38% acceptance rate)
Vijaykrishnan, N., N. Ranganathan. December 1998. Object Addressing Support for a Java Processor. Proceedings of the Sixth International Conference on Advanced Computing. pp. 61-67. Pune, India. (Principal author)
Chandramouli, R., N Vijaykrishnan, N Ranganathan. September 1998. SPRT for Weibull Distributed Integrated Circuit Failures. Proceedings of SPIE on Microelectronic Manufacturing. pp. 147-158. (Equal contributions by authors)
Vijaykrishnan, N., N. Ranganathan, R. Gadekarla. July 1998. Object-Oriented Architectural Support for a Java Processor. Proceedings of ECOOP’98, the 12th European Conference on Object-Oriented Programming (ECOOP ’98). LNCS 1445:330-354. (Principal author) [24 accepted out of 124 submissions] (19% acceptance rate)
Ranganathan, N., N. Vijaykrishnan, N. Bhavanishankar. October 1996. A VLSI Array Architecture with Dynamic Clocking. Proceedings of International Conference on Computer Design. pp. 137-140. Austin, Texas. (Equal contributions by authors) [83 accepted out of 126 submissions] (65% acceptance rate)
Vijaykrishnan, N., N. Ranganathan, N. Bhavanishankar. September 1996. DFLAP: Dynamic Frequency Linear Array Processor. Proceedings of the International Conference on Image Processing. pp. 2:1007-1010. Switzerland. (Principal author) [781 accepted out of 1515 submissions] (52% acceptance rate)
Vijaykrishnan, N., R. Chandramouli, N. Ranganathan. May 1996. Functional Reconfiguration for Fault Tolerance: A New Approach. Proceedings of International Conference on Modelling, Simulation and Optimization. Australia. (Proceedings available on CD-Rom) (Equal contributions by authors)
Vijaykrishnan, N., N. Ranganathan. January 1996. SUBGEN: A Genetic Approach for Subcircuit Extraction. Proceedings of Ninth International Conference on VLSI Design. pp. 343-345. (Principal author)[91 accepted out of 137 submissions] (66% acceptance rate)
Venkateswaran, N., S. Pattabiraman, V. Srinivasan, N. Vijaykrishnan, S. Balamurugan. November 1993. A Unified Approach to VLSI Layout Automation and Algorithm Mapping on Processor Arrays. Proceedings V NASA VLSI Conference. pp. 11.5.1-11.5 (Contributing author)

Books.

Nicopoulos*, C., N. Vijaykrishnan, C. R. Das. October 2009. Network-on-Chip Architectures: A Holistic Design Exploration. 175 pages. (First author supervised by candidate)
Vijaykrishnan and M. Wolczko (editors). Java Microarchitectures. April 2002. Kluwer Academic.

Parts of Books.

Kaisheng Ma, Shuangchen Li, Vijaykrishnan Narayanan, Yuan Xie. 2020. Nonvolatile Processor Architecture Exploration for Energy-Harvesting Application Scenarios. In Embedded, Cyber-Physical, and IoT Systems. pp. 175-202 (Book Chapter)
Ahmedullah Aziz, Sandeep Krishna Thirumala, Danni Wang, Sumitha George, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan, Sumeet Kumar Gupta. 2019. Sensing in Ferroelectric Memories and Flip-Flops. In Sensing of Non-Volatile Memory Demystified. pp. 47-80. Springer. (Book Chapter)
Wu, X., Y. Xie, N. Vijaykrishnan. Thermal-aware 3D IC Designs. 3D Integration of Integrated Circuits. Chapter 14. pp. 313-334. Edited by C. S. Tan, K. N. Chen, S. J. Koester. Pan Stanford Publishing, Ltd. (Book chapter)
Eachempati*, S., R. Das, N. Vijaykrishnan, Y. Xie, S. Datta, C. R. Das. February 2011. HeTERO: Hybrid Topology Exploration for RF Based On Chip Networks. In Communication Architectures for Systems-on-Chip. L. Ayala, Editor. CRC Press. (First author co-supervised by candidate) (Book chapter)
Eachempati*, S., A. Gayasen*, N. Vijaykrishnan, M. J. Irwin. January 2011. Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs. To appear in Nanoelectronic Circuit Design. Jha, D. Chen, Editors. Springer. (First two authors co-supervised by candidate) (Book chapter)
Kumar*, V., K. Irick*, A. Maashri*, N. Vijaykrishnan. A Scalable Bandwidth-Aware Architecture for Connected Component Labeling. To appear in Very Large Scale Integration Systems: Emerging Trends & Challenges. N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Editors. Springer. (First author co-supervised and second and third authors supervised by candidate) (Book chapter)
Eachempati*, S., D. Park, R. Das, A. K. Mishra, N. Vijaykrishnan, Y. Xie, C. R. Das. December 2010. Three-Dimensional On-Chip Interconnect Architectures. Designing Network On-Chip Architectures in the Nanoscale Era. Flich, D. Bertozzi, Editors. Chapman & Hall/CRC Computational Science. (First author co-supervised by candidate)
Maashri*, A., G. Sun, X. Dong, Y. Xie, N. Vijaykrishnan. November 2010. Influence of Stacked 3D Memory/Cache Architectures on GPUs. 3D Integration for NoC-based SoC Architectures. Chapter 11, pp. 249-272. Sheibanyrad, F. Pétrot, A. Jantsch, Editors. Springer. (First author supervised by candidate)
Yanamandra*, A., S. Eachempati*, N. Vijaykrishnan, M. J. Irwin. Reliability Aware Power Optimizations in DVFS-based On-Chip Networks. Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication. Chapter 11, pp. 277-292. J-S. Shen, P-A. Hsiung, Editors. (First two authors co-supervised by candidate) (Book chapter)
Xie, Y., N. Vijaykrishnan, C. R. Das. 2009. Three-Dimensional Network-on-Chip Architectures. Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. Chapter 8, pp. 189-218. Xie, J. Cong, S. Sapatnekar, Editors. Springer.
Theocharides*, T., C. Nicopoulos*, K. Irick*, N. Vijaykrishnan, M. J. Irwin. An Exploration of Hardware Architectures for Face Detection. The VLSI Handbook, Second Edition. Chapter 83, pp. 1-27. (First author co-supervised and second and third authors supervised by candidate)
Gayasen*, A., N. Vijaykrishnan. Architecture and Design Flow Optimizations for Power-Aware FPGAs. The VLSI Handbook, Second Edition. Chapter 20, pp. 1-15. (First author co-supervised by candidate)
Degalahal*, V., R. Ramanarayanan*, N. Vijaykrishnan, Y. Xie and M. J. Irwin. May 2006. Effect of Power Optimizations on Soft Error Rate. VLSI-SoCc: From Systems to Chips. Edited by M. Glesner, Eveking, L. Indrusiak, V. Mooney, R. Reis. (First and second authors supervised by candidate) (Book chapter)
Hu*, J. S., G. Chen, M. Kandemir, N. Vijaykrishnan. Software Power Optimisation. System on Chip: Next Generation Electronics. pp. 289-316. Edited by Bashir M. Al-Hashimi. (First author supervised by candidate) (Book chapter)
Kadayif, I., M. Kandemir, A. Choudhary, M. Karakoy, N. Vijaykrishnan, M. J. Irwin. Compiler-directed Communication Energy Optimizations for Microsensor Networks. Frontiers in Distributed Sensor Networks. pp. 711-734. Edited by R. Brooks and R. Iyengar. CRC Press. (Book chapter)
Saputra, H., N. Vijaykrishnan, M. Kandemir, R. Brooks, M. J. Irwin. An Energy-aware Approach for Sensor Data Communication. Frontiers in Distributed Sensor Networks. pp. 697-720. Edited by R. Brooks and R. Iyengar. CRC Press. (Book chapter) (First author co-supervised by candidate)
Vijaykrishnan, N., M. J. Irwin, M. Kandemir, L. Li, G. Chen, B. Kang. Designing Energy-aware Sensor Systems. Frontiers in Distributed Sensor Networks. pp. 653-666. Edited by R. Brooks and R. Iyengar. CRC Press. (Principal author) (Fourth and sixth authors co-supervised by candidate) (Book chapter)
Theocharides, T., G. Link, N. Vijaykrishnan, M. J. Irwin. Networks on Chip: Interconnects for the Next Generation Systems on Chip. Advances in Computers 63(1):35-89. Edited by M. Zelkowtiz and A. R. Hurson. (First author co-supervised and second author supervised by candidate)
Irwin, M. J., L. Benini, N. Vijaykrishnan, M. Kandemir. September 2004. Techniques for Designing Energy-aware MPSoCs. Multiprocessor Systems-on-Chips. Chapter 2, pp. 21-47. Edited by A. Jerraya and W. Wolf. (Book chapter) (Equal contributions)
Kadayif, I., M. Kandemir, N. Vijaykrishnan, M. J. Irwin, I. Kolcu. 2004. Reducing Energy Consumption in Chip Multiprocessors using Workload Variation. Ultra-Low Power Electronics and Design. pp. 123-140. Edited by E. Macii. (Book chapter)
Vijaykrishnan, N., M. Kandemir, A. Sivasubramaniam, M. J. Irwin. Tools and Techniques for Integrated Hardware-Software Energy Optimizations. Book Chapter for Power Aware Design Methodologies. pp. 277-295. Edited by Jan M. Rabaey and Massoud Pedram. Kluwer Academic. (Invited) (Equal Contributions by Authors)
Kandemir, M., N. Vijaykrishnan, M. J. Irwin. Compiler Optimizations for Low-Power Systems. Book Chapter for Power Aware Computing. Edited by R. Graybill and R. Melhem. Kluwer Academic/Plenum Publishers. pp. 191-210. (Equal contributions by authors)
Li, T., L. K. John, N. Vijaykrishnan, A. Sivasubramaniam. May 2001. Characterizing Operating System Activity in SPECjvm98 Benchmarks. Book Chapter for Characterization of Contemporary Workloads. 53-82. Kluwer Academic. Edited by L. K. John and A. M. Grizzaffi-Maynard. (Contributing author)
Kim, H. S., M. Kandemir, N. Vijaykrishnan, M. J. Irwin. May 2001. Characterization of Memory Energy Behavior. Book Chapter for Characterization of Contemporary Workloads. 165-180. Kluwer Academic. Edited by L. K. John and A. M. Grizzaffi-Maynard. (First author co-supervised by candidate)

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